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e25ded1888
I noticed unnecessary 'sbb' instructions in D30472 and while looking at 'ptest' codegen recently. This happens because we were transforming any 'setb' - even when we only wanted a single-bit result. This patch moves those transforms under visitAdd/visitSub, so we we're only creating sbb/adc when it is a win. I don't know why we need a SETCC_CARRY node type, but I'm not proposing to change that existing behavior in this patch. Also, I'm skeptical that sbb/adc are a win for all micro-arches, so I added comments to the test files where this transform still fires. The test changes here are all cases where we no longer produce sbb/adc. Avoiding partial register stalls (generating an xor to clear a register) is not handled in some cases, but that's a separate issue. Differential Revision: https://reviews.llvm.org/D30611 llvm-svn: 297586
93 lines
2.3 KiB
LLVM
93 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
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; rdar://7329206
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; Use sbb x, x to materialize carry bit in a GPR. The value is either
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; all 1's or all 0's.
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define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
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; CHECK-LABEL: t1:
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; CHECK: ## BB#0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: cmpl $26, %edi
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; CHECK-NEXT: seta %al
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; CHECK-NEXT: shll $5, %eax
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; CHECK-NEXT: retq
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%t0 = icmp ugt i16 %x, 26
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%if = select i1 %t0, i16 32, i16 0
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ret i16 %if
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}
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define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp {
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; CHECK-LABEL: t2:
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; CHECK: ## BB#0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: cmpl $26, %edi
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; CHECK-NEXT: setb %al
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; CHECK-NEXT: shll $5, %eax
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; CHECK-NEXT: retq
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%t0 = icmp ult i16 %x, 26
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%if = select i1 %t0, i16 32, i16 0
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ret i16 %if
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}
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define i64 @t3(i64 %x) nounwind readnone ssp {
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; CHECK-LABEL: t3:
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; CHECK: ## BB#0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: cmpq $18, %rdi
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; CHECK-NEXT: setb %al
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; CHECK-NEXT: shlq $6, %rax
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; CHECK-NEXT: retq
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%t0 = icmp ult i64 %x, 18
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%if = select i1 %t0, i64 64, i64 0
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ret i64 %if
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}
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@v4 = common global i32 0, align 4
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define i32 @t4(i32 %a) {
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; CHECK-LABEL: t4:
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; CHECK: ## BB#0:
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; CHECK-NEXT: movq _v4@{{.*}}(%rip), %rax
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; CHECK-NEXT: cmpl $1, (%rax)
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; CHECK-NEXT: movw $1, %ax
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; CHECK-NEXT: adcw $0, %ax
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; CHECK-NEXT: shll $16, %eax
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; CHECK-NEXT: retq
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%t0 = load i32, i32* @v4, align 4
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%not.tobool = icmp eq i32 %t0, 0
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%conv.i = sext i1 %not.tobool to i16
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%call.lobit = lshr i16 %conv.i, 15
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%add.i.1 = add nuw nsw i16 %call.lobit, 1
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%conv4.2 = zext i16 %add.i.1 to i32
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%add = shl nuw nsw i32 %conv4.2, 16
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ret i32 %add
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}
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define i8 @t5(i32 %a) #0 {
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; CHECK-LABEL: t5:
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; CHECK: ## BB#0:
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: setns %al
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; CHECK-NEXT: retq
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%.lobit = lshr i32 %a, 31
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%trunc = trunc i32 %.lobit to i8
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%.not = xor i8 %trunc, 1
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ret i8 %.not
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}
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define zeroext i1 @t6(i32 %a) #0 {
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; CHECK-LABEL: t6:
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; CHECK: ## BB#0:
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; CHECK-NEXT: testl %edi, %edi
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; CHECK-NEXT: setns %al
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; CHECK-NEXT: retq
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%.lobit = lshr i32 %a, 31
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%trunc = trunc i32 %.lobit to i1
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%.not = xor i1 %trunc, 1
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ret i1 %.not
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}
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attributes #0 = { "target-cpu"="skylake-avx512" }
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