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llvm-mirror/test/CodeGen/AArch64/GlobalISel/legalize-div.mir
Matthias Braun 075724a5d9 MIRTests: Remove unnecessary 2>&1 redirection
llc mir output goes to stdout nowadays, so the 2>&1 is not necessary
anymore for most tests.

llvm-svn: 295859
2017-02-22 18:47:41 +00:00

43 lines
1.0 KiB
YAML

# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64--"
define void @test_div() {
entry:
ret void
}
...
---
name: test_div
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.0.entry:
liveins: %x0, %x1, %x2, %x3
%0(s64) = COPY %x0
%1(s64) = COPY %x1
%2(s8) = G_TRUNC %0
%3(s8) = G_TRUNC %1
; CHECK: [[LHS32:%[0-9]+]](s32) = G_SEXT %2
; CHECK: [[RHS32:%[0-9]+]](s32) = G_SEXT %3
; CHECK: [[QUOT32:%[0-9]+]](s32) = G_SDIV [[LHS32]], [[RHS32]]
; CHECK: [[RES:%[0-9]+]](s8) = G_TRUNC [[QUOT32]]
%4(s8) = G_SDIV %2, %3
; CHECK: [[LHS32:%[0-9]+]](s32) = G_ZEXT %2
; CHECK: [[RHS32:%[0-9]+]](s32) = G_ZEXT %3
; CHECK: [[QUOT32:%[0-9]+]](s32) = G_UDIV [[LHS32]], [[RHS32]]
; CHECK: [[RES:%[0-9]+]](s8) = G_TRUNC [[QUOT32]]
%5(s8) = G_UDIV %2, %3
...