Amara Emerson d83de2e66b [AArch64][GlobalISel] Make G_VECREDUCE_ADD of <2 x s32> legal.		2021-02-19 14:28:21 -08:00
..
AArch64	[AArch64][GlobalISel] Make G_VECREDUCE_ADD of <2 x s32> legal.	2021-02-19 14:28:21 -08:00
AMDGPU	[MemCopyOpt] Enable MemorySSA by default	2021-02-19 18:06:25 +01:00
ARC
ARM	Revert "[ARM] Expand the range of allowed post-incs in load/store optimizer"	2021-02-19 13:15:10 +00:00
AVR	[AVR] Fix a bug in 16-bit shifts	2021-02-14 11:54:55 +08:00
BPF
Generic
Hexagon
Inputs
Lanai
Mips
MIR	Make fixed-abi default for AMD HSA OS	2021-02-19 15:05:25 +00:00
MSP430
NVPTX
PowerPC	[PowerPC][AIX] Add support for vector arg passing on the stack.	2021-02-18 13:32:40 -05:00
RISCV	[RISCV] Prevent selecting a 0 VL to X0 for the segment load/store intrinsics.	2021-02-19 10:07:12 -08:00
SPARC
SystemZ	[SystemZ] Separate LoZ ELF specifics in tablegen.	2021-02-17 16:11:58 -05:00
Thumb
Thumb2	Revert "[ARM] Expand the range of allowed post-incs in load/store optimizer"	2021-02-19 13:15:10 +00:00
VE
WebAssembly	[WebAssembly] Handle multiple EH_LABELs in EH pad	2021-02-18 10:18:00 -08:00
WinCFGuard
WinEH
X86	[X86] Regenerate 2007-06-28-X86-64-isel.ll	2021-02-19 18:35:15 +00:00
XCore