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https://github.com/RPCS3/llvm-mirror.git
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c4ee204f5c
Allocating larger register classes first should give better allocation results (and more importantly for myself, make the lit tests more stable with respect to scheduler changes). Patch by Matthias Braun llvm-svn: 270312
348 lines
13 KiB
LLVM
348 lines
13 KiB
LLVM
;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=SI
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=VI
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; Check that WQM isn't triggered by image load/store intrinsics.
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;
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;CHECK-LABEL: {{^}}test1:
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;CHECK-NOT: s_wqm
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define amdgpu_ps <4 x float> @test1(<8 x i32> inreg %rsrc, <4 x i32> %c) {
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main_body:
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%tex = call <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
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call void @llvm.amdgcn.image.store.v4i32(<4 x float> %tex, <4 x i32> %c, <8 x i32> %rsrc, i32 15, i1 0, i1 0, i1 0, i1 0)
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ret <4 x float> %tex
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}
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; Check that WQM is triggered by image samples and left untouched for loads...
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;
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;CHECK-LABEL: {{^}}test2:
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;CHECK-NEXT: ; %main_body
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;CHECK-NEXT: s_wqm_b64 exec, exec
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;CHECK: image_sample
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;CHECK-NOT: exec
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;CHECK: _load_dword v0,
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define amdgpu_ps float @test2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) {
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main_body:
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%c.1 = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%c.2 = bitcast <4 x float> %c.1 to <4 x i32>
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%c.3 = extractelement <4 x i32> %c.2, i32 0
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%gep = getelementptr float, float addrspace(1)* %ptr, i32 %c.3
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%data = load float, float addrspace(1)* %gep
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ret float %data
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}
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; ... but disabled for stores (and, in this simple case, not re-enabled).
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;
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;CHECK-LABEL: {{^}}test3:
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;CHECK-NEXT: ; %main_body
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;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
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;CHECK-NEXT: s_wqm_b64 exec, exec
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;CHECK: image_sample
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;CHECK: s_and_b64 exec, exec, [[ORIG]]
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;CHECK: store
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;CHECK-NOT: exec
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define amdgpu_ps <4 x float> @test3(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <4 x i32> %c) {
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main_body:
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%tex = call <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32> %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%tex.1 = bitcast <4 x float> %tex to <4 x i32>
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%tex.2 = extractelement <4 x i32> %tex.1, i32 0
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%gep = getelementptr float, float addrspace(1)* %ptr, i32 %tex.2
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%wr = extractelement <4 x float> %tex, i32 1
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store float %wr, float addrspace(1)* %gep
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ret <4 x float> %tex
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}
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; Check that WQM is re-enabled when required.
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;
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;CHECK-LABEL: {{^}}test4:
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;CHECK-NEXT: ; %main_body
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;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
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;CHECK-NEXT: s_wqm_b64 exec, exec
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;CHECK: v_mul_lo_i32 [[MUL:v[0-9]+]], v0, v1
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;CHECK: s_and_b64 exec, exec, [[ORIG]]
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;CHECK: store
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;CHECK: s_wqm_b64 exec, exec
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;CHECK: image_sample v[0:3], [[MUL]], s[0:7], s[8:11] dmask:0xf
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define amdgpu_ps <4 x float> @test4(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %c, i32 %d, float %data) {
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main_body:
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%c.1 = mul i32 %c, %d
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%gep = getelementptr float, float addrspace(1)* %ptr, i32 %c.1
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store float %data, float addrspace(1)* %gep
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%tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %c.1, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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ret <4 x float> %tex
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}
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; Check a case of one branch of an if-else requiring WQM, the other requiring
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; exact.
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;
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; Note: In this particular case, the save-and-restore could be avoided if the
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; analysis understood that the two branches of the if-else are mutually
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; exclusive.
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;
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;CHECK-LABEL: {{^}}test_control_flow_0:
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;CHECK-NEXT: ; %main_body
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;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
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;CHECK-NEXT: s_wqm_b64 exec, exec
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;CHECK: %ELSE
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;CHECK: s_and_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]], [[ORIG]]
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;CHECK: store
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;CHECK: s_mov_b64 exec, [[SAVED]]
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;CHECK: %IF
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;CHECK: image_sample
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define amdgpu_ps float @test_control_flow_0(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %c, i32 %z, float %data) {
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main_body:
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%cmp = icmp eq i32 %z, 0
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br i1 %cmp, label %IF, label %ELSE
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IF:
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%tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%data.if = extractelement <4 x float> %tex, i32 0
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br label %END
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ELSE:
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%gep = getelementptr float, float addrspace(1)* %ptr, i32 %c
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store float %data, float addrspace(1)* %gep
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br label %END
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END:
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%r = phi float [ %data.if, %IF ], [ %data, %ELSE ]
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ret float %r
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}
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; Reverse branch order compared to the previous test.
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;
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;CHECK-LABEL: {{^}}test_control_flow_1:
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;CHECK-NEXT: ; %main_body
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;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
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;CHECK-NEXT: s_wqm_b64 exec, exec
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;CHECK: %IF
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;CHECK: image_sample
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;CHECK: %Flow
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;CHECK-NEXT: s_or_saveexec_b64 [[SAVED:s\[[0-9]+:[0-9]+\]]],
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;CHECK-NEXT: s_and_b64 exec, exec, [[ORIG]]
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;CHECK-NEXT: s_and_b64 [[SAVED]], exec, [[SAVED]]
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;CHECK-NEXT: s_xor_b64 exec, exec, [[SAVED]]
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;CHECK-NEXT: %ELSE
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;CHECK: store
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;CHECK: %END
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define amdgpu_ps float @test_control_flow_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %c, i32 %z, float %data) {
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main_body:
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%cmp = icmp eq i32 %z, 0
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br i1 %cmp, label %ELSE, label %IF
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IF:
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%tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %c, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%data.if = extractelement <4 x float> %tex, i32 0
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br label %END
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ELSE:
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%gep = getelementptr float, float addrspace(1)* %ptr, i32 %c
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store float %data, float addrspace(1)* %gep
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br label %END
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END:
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%r = phi float [ %data.if, %IF ], [ %data, %ELSE ]
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ret float %r
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}
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; Check that branch conditions are properly marked as needing WQM...
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;
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;CHECK-LABEL: {{^}}test_control_flow_2:
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;CHECK-NEXT: ; %main_body
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;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
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;CHECK-NEXT: s_wqm_b64 exec, exec
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;CHECK: s_and_b64 exec, exec, [[ORIG]]
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;CHECK: store
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;CHECK: s_wqm_b64 exec, exec
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;CHECK: load
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;CHECK: s_and_b64 exec, exec, [[ORIG]]
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;CHECK: store
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;CHECK: s_wqm_b64 exec, exec
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;CHECK: v_cmp
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define amdgpu_ps <4 x float> @test_control_flow_2(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <3 x i32> %idx, <2 x float> %data, i32 %coord) {
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main_body:
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%idx.1 = extractelement <3 x i32> %idx, i32 0
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%gep.1 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.1
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%data.1 = extractelement <2 x float> %data, i32 0
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store float %data.1, float addrspace(1)* %gep.1
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; The load that determines the branch (and should therefore be WQM) is
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; surrounded by stores that require disabled WQM.
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%idx.2 = extractelement <3 x i32> %idx, i32 1
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%gep.2 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.2
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%z = load float, float addrspace(1)* %gep.2
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%idx.3 = extractelement <3 x i32> %idx, i32 2
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%gep.3 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.3
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%data.3 = extractelement <2 x float> %data, i32 1
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store float %data.3, float addrspace(1)* %gep.3
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%cc = fcmp ogt float %z, 0.0
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br i1 %cc, label %IF, label %ELSE
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IF:
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%coord.IF = mul i32 %coord, 3
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br label %END
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ELSE:
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%coord.ELSE = mul i32 %coord, 4
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br label %END
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END:
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%coord.END = phi i32 [ %coord.IF, %IF ], [ %coord.ELSE, %ELSE ]
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%tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord.END, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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ret <4 x float> %tex
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}
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; ... but only if they really do need it.
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;
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;CHECK-LABEL: {{^}}test_control_flow_3:
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;CHECK-NEXT: ; %main_body
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;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
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;CHECK-NEXT: s_wqm_b64 exec, exec
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;CHECK: image_sample
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;CHECK: s_and_b64 exec, exec, [[ORIG]]
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;CHECK: store
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;CHECK: load
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;CHECK: store
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;CHECK: v_cmp
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define amdgpu_ps float @test_control_flow_3(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <3 x i32> %idx, <2 x float> %data, i32 %coord) {
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main_body:
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%tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%tex.1 = extractelement <4 x float> %tex, i32 0
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%idx.1 = extractelement <3 x i32> %idx, i32 0
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%gep.1 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.1
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%data.1 = extractelement <2 x float> %data, i32 0
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store float %data.1, float addrspace(1)* %gep.1
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%idx.2 = extractelement <3 x i32> %idx, i32 1
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%gep.2 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.2
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%z = load float, float addrspace(1)* %gep.2
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%idx.3 = extractelement <3 x i32> %idx, i32 2
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%gep.3 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.3
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%data.3 = extractelement <2 x float> %data, i32 1
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store float %data.3, float addrspace(1)* %gep.3
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%cc = fcmp ogt float %z, 0.0
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br i1 %cc, label %IF, label %ELSE
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IF:
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%tex.IF = fmul float %tex.1, 3.0
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br label %END
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ELSE:
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%tex.ELSE = fmul float %tex.1, 4.0
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br label %END
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END:
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%tex.END = phi float [ %tex.IF, %IF ], [ %tex.ELSE, %ELSE ]
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ret float %tex.END
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}
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; Another test that failed at some point because of terminator handling.
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;
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;CHECK-LABEL: {{^}}test_control_flow_4:
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;CHECK-NEXT: ; %main_body
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;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
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;CHECK-NEXT: s_wqm_b64 exec, exec
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;CHECK: %IF
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;CHECK: load
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;CHECK: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[ORIG]]
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;CHECK: store
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;CHECK: s_mov_b64 exec, [[SAVE]]
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;CHECK: %END
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;CHECK: image_sample
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define amdgpu_ps <4 x float> @test_control_flow_4(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %coord, i32 %y, float %z) {
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main_body:
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%cond = icmp eq i32 %y, 0
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br i1 %cond, label %IF, label %END
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IF:
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%data = load float, float addrspace(1)* %ptr
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%gep = getelementptr float, float addrspace(1)* %ptr, i32 1
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store float %data, float addrspace(1)* %gep
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br label %END
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END:
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%tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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ret <4 x float> %tex
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}
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; Kill is performed in WQM mode so that uniform kill behaves correctly ...
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;
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;CHECK-LABEL: {{^}}test_kill_0:
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;CHECK-NEXT: ; %main_body
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;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
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;CHECK-NEXT: s_wqm_b64 exec, exec
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;CHECK: image_sample
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;CHECK: s_and_b64 exec, exec, [[ORIG]]
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;SI: buffer_store_dword
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;VI: flat_store_dword
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;CHECK: s_wqm_b64 exec, exec
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;CHECK: v_cmpx_
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;CHECK: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[ORIG]]
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;SI: buffer_store_dword
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;VI: flat_store_dword
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;CHECK: s_mov_b64 exec, [[SAVE]]
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;CHECK: image_sample
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define amdgpu_ps <4 x float> @test_kill_0(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, <2 x i32> %idx, <2 x float> %data, i32 %coord, i32 %coord2, float %z) {
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main_body:
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%tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%idx.0 = extractelement <2 x i32> %idx, i32 0
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%gep.0 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.0
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%data.0 = extractelement <2 x float> %data, i32 0
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store float %data.0, float addrspace(1)* %gep.0
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call void @llvm.AMDGPU.kill(float %z)
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%idx.1 = extractelement <2 x i32> %idx, i32 1
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%gep.1 = getelementptr float, float addrspace(1)* %ptr, i32 %idx.1
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%data.1 = extractelement <2 x float> %data, i32 1
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store float %data.1, float addrspace(1)* %gep.1
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%tex2 = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord2, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%out = fadd <4 x float> %tex, %tex2
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ret <4 x float> %out
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}
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; ... but only if WQM is necessary.
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;
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; CHECK-LABEL: {{^}}test_kill_1:
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; CHECK-NEXT: ; %main_body
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; CHECK: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
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; CHECK: s_wqm_b64 exec, exec
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; CHECK: image_sample
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; CHECK: s_and_b64 exec, exec, [[ORIG]]
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; SI: buffer_store_dword
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; VI: flat_store_dword
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; CHECK-NOT: wqm
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; CHECK: v_cmpx_
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define amdgpu_ps <4 x float> @test_kill_1(<8 x i32> inreg %rsrc, <4 x i32> inreg %sampler, float addrspace(1)* inreg %ptr, i32 %idx, float %data, i32 %coord, i32 %coord2, float %z) {
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main_body:
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%tex = call <4 x float> @llvm.SI.image.sample.i32(i32 %coord, <8 x i32> %rsrc, <4 x i32> %sampler, i32 15, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
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%gep = getelementptr float, float addrspace(1)* %ptr, i32 %idx
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store float %data, float addrspace(1)* %gep
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call void @llvm.AMDGPU.kill(float %z)
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ret <4 x float> %tex
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}
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declare void @llvm.amdgcn.image.store.v4i32(<4 x float>, <4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1
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declare <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #2
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declare <4 x float> @llvm.SI.image.sample.i32(i32, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #3
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declare <4 x float> @llvm.SI.image.sample.v4i32(<4 x i32>, <8 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i32, i32) #3
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declare void @llvm.AMDGPU.kill(float)
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #1 = { nounwind }
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attributes #2 = { nounwind readonly }
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attributes #3 = { nounwind readnone }
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