| .. |
|
AsmParser
|
[Aarch64] Adding support for Armv9-A Realm Management Extension
|
2021-06-28 13:45:22 +01:00 |
|
Disassembler
|
[AArch64] Adding the v8.7-A LD64B/ST64B Accelerator extension
|
2020-12-17 13:46:23 +00:00 |
|
GISel
|
GlobalISel: Use LLT in call lowering callbacks
|
2021-07-01 12:15:54 -04:00 |
|
MCTargetDesc
|
[AArch64][X86] Allow 64-bit label differences lower to IMAGE_REL_*_REL32
|
2021-06-21 14:32:25 -07:00 |
|
TargetInfo
|
llvmbuildectomy - replace llvm-build by plain cmake
|
2020-11-13 10:35:24 +01:00 |
|
Utils
|
[ARM][AArch64] Adding basic support for the v8.7-A architecture
|
2020-12-17 13:45:08 +00:00 |
|
AArch64.h
|
[AArch64][GlobalISel] Create a new minimal combiner pass just for -O0.
|
2021-05-07 17:01:27 -07:00 |
|
AArch64.td
|
[Aarch64] Adding support for Armv9-A Realm Management Extension
|
2021-06-28 13:45:22 +01:00 |
|
AArch64A53Fix835769.cpp
|
|
|
|
AArch64A57FPLoadBalancing.cpp
|
|
|
|
AArch64AdvSIMDScalarPass.cpp
|
|
|
|
AArch64AsmPrinter.cpp
|
[NFC] Refactor how CFI section types are represented in AsmPrinter
|
2021-04-28 09:04:04 +05:30 |
|
AArch64BranchTargets.cpp
|
[AArch64] Fix for BTI landing pad insertion with PAC-RET+bkey.
|
2021-04-23 10:07:25 +02:00 |
|
AArch64CallingConvention.cpp
|
[clang][AArch64] Correctly align HFA arguments when passed on the stack
|
2021-04-15 22:58:14 +01:00 |
|
AArch64CallingConvention.h
|
|
|
|
AArch64CallingConvention.td
|
IR/AArch64/X86: add "swifttailcc" calling convention.
|
2021-05-17 10:48:34 +01:00 |
|
AArch64CleanupLocalDynamicTLSPass.cpp
|
|
|
|
AArch64CollectLOH.cpp
|
[AArch64] Fix emitting an AdrpAddLdr LOH when there's a potential clobber of the
|
2021-03-01 13:52:57 -08:00 |
|
AArch64Combine.td
|
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX
|
2021-06-28 09:06:44 -04:00 |
|
AArch64CompressJumpTables.cpp
|
[AArch64] Don't try to compress jump tables if there are any inline asm instructions.
|
2020-12-10 12:20:02 -08:00 |
|
AArch64CondBrTuning.cpp
|
|
|
|
AArch64ConditionalCompares.cpp
|
|
|
|
AArch64ConditionOptimizer.cpp
|
|
|
|
AArch64DeadRegisterDefinitionsPass.cpp
|
|
|
|
AArch64ExpandImm.cpp
|
[AArch64] Fix some coding standard issues related to namespace llvm
|
2021-05-05 15:27:16 -07:00 |
|
AArch64ExpandImm.h
|
|
|
|
AArch64ExpandPseudoInsts.cpp
|
IR+AArch64: add a "swiftasync" argument attribute.
|
2021-05-14 11:43:58 +01:00 |
|
AArch64FalkorHWPFFix.cpp
|
|
|
|
AArch64FastISel.cpp
|
IR+AArch64: add a "swiftasync" argument attribute.
|
2021-05-14 11:43:58 +01:00 |
|
AArch64FrameLowering.cpp
|
[AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP)
|
2021-06-24 18:24:32 +01:00 |
|
AArch64FrameLowering.h
|
IR+AArch64: add a "swiftasync" argument attribute.
|
2021-05-14 11:43:58 +01:00 |
|
AArch64GenRegisterBankInfo.def
|
AArch64: support i128 cmpxchg in GlobalISel.
|
2021-05-14 10:41:38 +01:00 |
|
AArch64InstrAtomics.td
|
|
|
|
AArch64InstrFormats.td
|
IR+AArch64: add a "swiftasync" argument attribute.
|
2021-05-14 11:43:58 +01:00 |
|
AArch64InstrGISel.td
|
AArch64: support i128 cmpxchg in GlobalISel.
|
2021-05-14 10:41:38 +01:00 |
|
AArch64InstrInfo.cpp
|
[AArch64][v8.3A] Avoid inserting implicit landing pads (PACI*SP)
|
2021-06-24 18:24:32 +01:00 |
|
AArch64InstrInfo.h
|
[AArch64] Adds a pre-indexed paired Load/Store optimization for LDR-STR.
|
2021-04-30 17:29:58 +01:00 |
|
AArch64InstrInfo.td
|
[ISel] Port AArch64 SABD and UABD to DAGCombine
|
2021-06-26 19:34:16 +01:00 |
|
AArch64ISelDAGToDAG.cpp
|
Rename MachineMemOperand::getOrdering -> getSuccessOrdering.
|
2021-06-21 16:49:27 -07:00 |
|
AArch64ISelLowering.cpp
|
[AArch64] Use custom lowering for fp16 vector copysign.
|
2021-07-02 11:15:30 +01:00 |
|
AArch64ISelLowering.h
|
[AArch64] Optimize SVE bitcasts of unpacked types.
|
2021-07-01 15:35:48 -07:00 |
|
AArch64LoadStoreOptimizer.cpp
|
Revert "[AArch64LoadStoreOptimizer] Recommit: Generate more STPs by renaming registers earlier"
|
2021-06-23 09:54:16 +03:00 |
|
AArch64LowerHomogeneousPrologEpilog.cpp
|
[CodeGen] Add missing includes (NFC)
|
2021-06-06 15:48:27 +02:00 |
|
AArch64MachineFunctionInfo.cpp
|
[llvm] Rename StringRef _lower() method calls to _insensitive()
|
2021-06-25 00:22:01 +03:00 |
|
AArch64MachineFunctionInfo.h
|
IR/AArch64/X86: add "swifttailcc" calling convention.
|
2021-05-17 10:48:34 +01:00 |
|
AArch64MacroFusion.cpp
|
[AArch64] Fix some coding standard issues related to namespace llvm
|
2021-05-05 15:27:16 -07:00 |
|
AArch64MacroFusion.h
|
[llvm] Add missing header guards (NFC)
|
2021-01-30 09:53:42 -08:00 |
|
AArch64MCInstLower.cpp
|
[AArch64][ELF] Prefer to lower MC_GlobalAddress operands to .Lfoo$local
|
2021-05-07 09:44:26 -07:00 |
|
AArch64MCInstLower.h
|
|
|
|
AArch64PBQPRegAlloc.cpp
|
[NFCI] Move DEBUG_TYPE definition below #includes
|
2021-05-30 17:31:01 +08:00 |
|
AArch64PBQPRegAlloc.h
|
|
|
|
AArch64PerfectShuffle.h
|
|
|
|
AArch64PfmCounters.td
|
|
|
|
AArch64PromoteConstant.cpp
|
|
|
|
AArch64RedundantCopyElimination.cpp
|
[AArch64] Fix Copy Elemination for negative values
|
2020-12-18 13:30:46 +00:00 |
|
AArch64RegisterBanks.td
|
AArch64: support i128 cmpxchg in GlobalISel.
|
2021-05-14 10:41:38 +01:00 |
|
AArch64RegisterInfo.cpp
|
IR/AArch64/X86: add "swifttailcc" calling convention.
|
2021-05-17 10:48:34 +01:00 |
|
AArch64RegisterInfo.h
|
Change materializeFrameBaseRegister() to return register
|
2021-01-22 15:51:06 -08:00 |
|
AArch64RegisterInfo.td
|
[AArch64] Add a GPR64x8 register class
|
2020-12-17 13:45:46 +00:00 |
|
AArch64SchedA53.td
|
|
|
|
AArch64SchedA55.td
|
[MCA] Disable RCU for InOrderIssueStage
|
2021-03-24 13:54:04 +03:00 |
|
AArch64SchedA57.td
|
[AARCH64] Improve accumulator forwarding for Cortex-A57 model
|
2021-01-04 10:58:43 +00:00 |
|
AArch64SchedA57WriteRes.td
|
[AARCH64] Improve accumulator forwarding for Cortex-A57 model
|
2021-01-04 10:58:43 +00:00 |
|
AArch64SchedA64FX.td
|
[AArch64] Add Fujitsu A64FX scheduling model
|
2021-01-15 17:14:04 +09:00 |
|
AArch64SchedCyclone.td
|
|
|
|
AArch64SchedExynosM3.td
|
|
|
|
AArch64SchedExynosM4.td
|
|
|
|
AArch64SchedExynosM5.td
|
|
|
|
AArch64SchedFalkor.td
|
|
|
|
AArch64SchedFalkorDetails.td
|
|
|
|
AArch64SchedKryo.td
|
|
|
|
AArch64SchedKryoDetails.td
|
|
|
|
AArch64SchedPredExynos.td
|
|
|
|
AArch64SchedPredicates.td
|
|
|
|
AArch64SchedThunderX2T99.td
|
|
|
|
AArch64SchedThunderX3T110.td
|
|
|
|
AArch64SchedThunderX.td
|
|
|
|
AArch64SchedTSV110.td
|
[AArch64] Add pipeline model for HiSilicon's TSV110
|
2020-11-07 01:23:00 +03:00 |
|
AArch64Schedule.td
|
|
|
|
AArch64SelectionDAGInfo.cpp
|
[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
|
2021-02-18 16:55:16 +00:00 |
|
AArch64SelectionDAGInfo.h
|
[AArch64][SVE] Add patterns to generate FMLA/FMLS/FNMLA/FNMLS/FMAD
|
2021-02-18 16:55:16 +00:00 |
|
AArch64SIMDInstrOpt.cpp
|
|
|
|
AArch64SLSHardening.cpp
|
[ARM][AArch64] SLSHardening: make non-comdat thunks possible
|
2021-05-20 17:07:05 +02:00 |
|
AArch64SpeculationHardening.cpp
|
|
|
|
AArch64StackTagging.cpp
|
[MTE] Remove redundant helper function.
|
2021-06-30 11:11:26 +01:00 |
|
AArch64StackTaggingPreRA.cpp
|
[AArch64] Fix some coding standard issues related to namespace llvm
|
2021-05-05 15:27:16 -07:00 |
|
AArch64StorePairSuppress.cpp
|
|
|
|
AArch64Subtarget.cpp
|
[AArch64][SVE] Wire up vscale_range attribute to SVE min/max vector queries
|
2021-06-21 13:00:36 +01:00 |
|
AArch64Subtarget.h
|
[Aarch64] Adding support for Armv9-A Realm Management Extension
|
2021-06-28 13:45:22 +01:00 |
|
AArch64SVEInstrInfo.td
|
[SVE] Selection failure with scalable insertelements
|
2021-06-16 15:38:31 +01:00 |
|
AArch64SystemOperands.td
|
[Aarch64] Adding support for Armv9-A Realm Management Extension
|
2021-06-28 13:45:22 +01:00 |
|
AArch64TargetMachine.cpp
|
[AArch64][SVE] Wire up vscale_range attribute to SVE min/max vector queries
|
2021-06-21 13:00:36 +01:00 |
|
AArch64TargetMachine.h
|
|
|
|
AArch64TargetObjectFile.cpp
|
|
|
|
AArch64TargetObjectFile.h
|
|
|
|
AArch64TargetTransformInfo.cpp
|
[AArch64][SVEIntrinsicOpts] Convect cntb/h/w/d to vscale intrinsic or constant.
|
2021-07-01 10:09:47 +08:00 |
|
AArch64TargetTransformInfo.h
|
[AArch64][SVE] Add support for fixed length MSCATTER/MGATHER
|
2021-07-01 12:13:59 +01:00 |
|
CMakeLists.txt
|
[AArch64][GlobalISel] Create a new minimal combiner pass just for -O0.
|
2021-05-07 17:01:27 -07:00 |
|
SVEInstrFormats.td
|
[AArch64][SVE] Add support for using reverse forms of SVE2 shifts
|
2021-06-04 12:56:53 +01:00 |
|
SVEIntrinsicOpts.cpp
|
[AArch64] Fix namespace issue. NFC
|
2021-05-06 11:16:07 -07:00 |
