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a2fcb7f104
Octeon branches (bbit0/bbit032/bbit1/bbit132) have an immediate operand, so it is legal to have such replacement within MipsBranchExpansion::replaceBranch(). According to the specification, a branch (e.g. bbit0 ) looks like: bbit0 rs p offset // p is an immediate operand if !rs<p> then branch Without this patch, an assertion triggers in the method, and the problem has been found in the real example. Differential Revision: https://reviews.llvm.org/D76842
106 lines
2.5 KiB
LLVM
106 lines
2.5 KiB
LLVM
;; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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;; Test that Octeon BBIT family of branch can be replaced by
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;; the long branch expansion pass.
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; RUN: llc -O3 -mtriple=mips64-octeon-linux -mcpu=octeon -force-mips-long-branch < %s -o - | FileCheck %s
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define i64 @bbit1(i64 %a) nounwind {
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; CHECK-LABEL: bbit1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: bbit0 $4, 3, .LBB0_2
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; CHECK-NEXT: nop
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: j .LBB0_3
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; CHECK-NEXT: nop
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; CHECK-NEXT: .LBB0_2: # %endif
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: daddiu $2, $zero, 12
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; CHECK-NEXT: .LBB0_3: # %if
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: daddiu $2, $zero, 48
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entry:
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%bit = and i64 %a, 8
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%res = icmp eq i64 %bit, 0
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br i1 %res, label %endif, label %if
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if:
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ret i64 48
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endif:
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ret i64 12
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}
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define i64 @bbit132(i64 %a) nounwind {
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; CHECK-LABEL: bbit132:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: bbit032 $4, 3, .LBB1_2
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; CHECK-NEXT: nop
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: j .LBB1_3
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; CHECK-NEXT: nop
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; CHECK-NEXT: .LBB1_2: # %endif
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: daddiu $2, $zero, 12
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; CHECK-NEXT: .LBB1_3: # %if
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: daddiu $2, $zero, 48
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entry:
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%bit = and i64 %a, 34359738368
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%res = icmp eq i64 %bit, 0
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br i1 %res, label %endif, label %if
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if:
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ret i64 48
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endif:
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ret i64 12
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}
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define i64 @bbit0(i64 %a) nounwind {
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; CHECK-LABEL: bbit0:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: bbit1 $4, 3, .LBB2_2
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; CHECK-NEXT: nop
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: j .LBB2_3
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; CHECK-NEXT: nop
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; CHECK-NEXT: .LBB2_2: # %endif
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: daddiu $2, $zero, 12
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; CHECK-NEXT: .LBB2_3: # %if
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: daddiu $2, $zero, 48
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entry:
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%bit = and i64 %a, 8
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%res = icmp ne i64 %bit, 0
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br i1 %res, label %endif, label %if
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if:
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ret i64 48
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endif:
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ret i64 12
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}
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define i64 @bbit032(i64 %a) nounwind {
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; CHECK-LABEL: bbit032:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: bbit132 $4, 3, .LBB3_2
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; CHECK-NEXT: nop
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: j .LBB3_3
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; CHECK-NEXT: nop
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; CHECK-NEXT: .LBB3_2: # %endif
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: daddiu $2, $zero, 12
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; CHECK-NEXT: .LBB3_3: # %if
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; CHECK-NEXT: jr $ra
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; CHECK-NEXT: daddiu $2, $zero, 48
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entry:
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%bit = and i64 %a, 34359738368
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%res = icmp ne i64 %bit, 0
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br i1 %res, label %endif, label %if
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if:
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ret i64 48
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endif:
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ret i64 12
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}
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