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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
162 lines
4.7 KiB
YAML
162 lines
4.7 KiB
YAML
# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=cortex-a57 -enable-unsafe-fp-math -machine-combiner-verify-pattern-order=true %s | FileCheck --check-prefixes=UNPROFITABLE,ALL %s
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# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=falkor -enable-unsafe-fp-math %s -machine-combiner-verify-pattern-order=true | FileCheck --check-prefixes=PROFITABLE,ALL %s
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# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=exynos-m1 -enable-unsafe-fp-math -machine-combiner-verify-pattern-order=true %s | FileCheck --check-prefixes=PROFITABLE,ALL %s
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# RUN: llc -run-pass=machine-combiner -o - -mtriple=aarch64-unknown-linux -mcpu=thunderx2t99 -enable-unsafe-fp-math -machine-combiner-verify-pattern-order=true %s | FileCheck --check-prefixes=PROFITABLE,ALL %s
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#
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name: f1_2s
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registers:
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- { id: 0, class: fpr64 }
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- { id: 1, class: fpr64 }
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- { id: 2, class: fpr64 }
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- { id: 3, class: fpr64 }
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- { id: 4, class: fpr64 }
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body: |
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bb.0.entry:
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%2:fpr64 = COPY $d2
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%1:fpr64 = COPY $d1
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%0:fpr64 = COPY $d0
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%3:fpr64 = FMULv2f32 %0, %1
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%4:fpr64 = FSUBv2f32 killed %3, %2
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$d0 = COPY %4
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RET_ReallyLR implicit $d0
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...
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# UNPROFITABLE-LABEL: name: f1_2s
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# UNPROFITABLE: %3:fpr64 = FMULv2f32 %0, %1
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# UNPROFITABLE-NEXT: FSUBv2f32 killed %3, %2
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#
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# PROFITABLE-LABEL: name: f1_2s
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# PROFITABLE: [[R1:%[0-9]+]]:fpr64 = FNEGv2f32 %2
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# PROFITABLE-NEXT: FMLAv2f32 killed [[R1]], %0, %1
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---
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name: f1_4s
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registers:
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- { id: 0, class: fpr128 }
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- { id: 1, class: fpr128 }
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- { id: 2, class: fpr128 }
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- { id: 3, class: fpr128 }
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- { id: 4, class: fpr128 }
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body: |
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bb.0.entry:
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%2:fpr128 = COPY $q2
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%1:fpr128 = COPY $q1
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%0:fpr128 = COPY $q0
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%3:fpr128 = FMULv4f32 %0, %1
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%4:fpr128 = FSUBv4f32 killed %3, %2
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$q0 = COPY %4
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RET_ReallyLR implicit $q0
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...
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# UNPROFITABLE-LABEL: name: f1_4s
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# UNPROFITABLE: %3:fpr128 = FMULv4f32 %0, %1
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# UNPROFITABLE-NEXT: FSUBv4f32 killed %3, %2
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#
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# PROFITABLE-LABEL: name: f1_4s
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# PROFITABLE: [[R1:%[0-9]+]]:fpr128 = FNEGv4f32 %2
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# PROFITABLE-NEXT: FMLAv4f32 killed [[R1]], %0, %1
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---
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name: f1_2d
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registers:
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- { id: 0, class: fpr128 }
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- { id: 1, class: fpr128 }
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- { id: 2, class: fpr128 }
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- { id: 3, class: fpr128 }
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- { id: 4, class: fpr128 }
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body: |
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bb.0.entry:
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%2:fpr128 = COPY $q2
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%1:fpr128 = COPY $q1
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%0:fpr128 = COPY $q0
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%3:fpr128 = FMULv2f64 %0, %1
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%4:fpr128 = FSUBv2f64 killed %3, %2
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$q0 = COPY %4
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RET_ReallyLR implicit $q0
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...
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# UNPROFITABLE-LABEL: name: f1_2d
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# UNPROFITABLE: %3:fpr128 = FMULv2f64 %0, %1
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# UNPROFITABLE-NEXT: FSUBv2f64 killed %3, %2
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#
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# PROFITABLE-LABEL: name: f1_2d
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# PROFITABLE: [[R1:%[0-9]+]]:fpr128 = FNEGv2f64 %2
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# PROFITABLE-NEXT: FMLAv2f64 killed [[R1]], %0, %1
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---
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name: f1_both_fmul_2s
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registers:
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- { id: 0, class: fpr64 }
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- { id: 1, class: fpr64 }
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- { id: 2, class: fpr64 }
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- { id: 3, class: fpr64 }
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- { id: 4, class: fpr64 }
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- { id: 5, class: fpr64 }
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- { id: 6, class: fpr64 }
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body: |
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bb.0.entry:
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%3:fpr64 = COPY $q3
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%2:fpr64 = COPY $q2
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%1:fpr64 = COPY $q1
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%0:fpr64 = COPY $q0
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%4:fpr64 = FMULv2f32 %0, %1
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%5:fpr64 = FMULv2f32 %2, %3
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%6:fpr64 = FSUBv2f32 killed %4, %5
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$q0 = COPY %6
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RET_ReallyLR implicit $q0
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...
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# ALL-LABEL: name: f1_both_fmul_2s
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# ALL: %4:fpr64 = FMULv2f32 %0, %1
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# ALL-NEXT: FMLSv2f32 killed %4, %2, %3
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---
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name: f1_both_fmul_4s
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registers:
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- { id: 0, class: fpr128 }
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- { id: 1, class: fpr128 }
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- { id: 2, class: fpr128 }
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- { id: 3, class: fpr128 }
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- { id: 4, class: fpr128 }
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- { id: 5, class: fpr128 }
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- { id: 6, class: fpr128 }
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body: |
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bb.0.entry:
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%3:fpr128 = COPY $q3
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%2:fpr128 = COPY $q2
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%1:fpr128 = COPY $q1
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%0:fpr128 = COPY $q0
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%4:fpr128 = FMULv4f32 %0, %1
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%5:fpr128 = FMULv4f32 %2, %3
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%6:fpr128 = FSUBv4f32 killed %4, %5
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$q0 = COPY %6
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RET_ReallyLR implicit $q0
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...
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# ALL-LABEL: name: f1_both_fmul_4s
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# ALL: %4:fpr128 = FMULv4f32 %0, %1
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# ALL-NEXT: FMLSv4f32 killed %4, %2, %3
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---
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name: f1_both_fmul_2d
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registers:
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- { id: 0, class: fpr128 }
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- { id: 1, class: fpr128 }
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- { id: 2, class: fpr128 }
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- { id: 3, class: fpr128 }
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- { id: 4, class: fpr128 }
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- { id: 5, class: fpr128 }
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- { id: 6, class: fpr128 }
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body: |
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bb.0.entry:
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%3:fpr128 = COPY $q3
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%2:fpr128 = COPY $q2
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%1:fpr128 = COPY $q1
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%0:fpr128 = COPY $q0
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%4:fpr128 = FMULv2f64 %0, %1
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%5:fpr128 = FMULv2f64 %2, %3
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%6:fpr128 = FSUBv2f64 killed %4, %5
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$q0 = COPY %6
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RET_ReallyLR implicit $q0
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...
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# ALL-LABEL: name: f1_both_fmul_2d
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# ALL: %4:fpr128 = FMULv2f64 %0, %1
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# ALL-NEXT: FMLSv2f64 killed %4, %2, %3
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