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https://github.com/RPCS3/llvm-mirror.git
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07186d14a9
Vector load/store instructions support an optional alignment field that the compiler can use to provide known alignment info to the hardware. If the field is used (and the information is correct), the hardware may be able (on some models) to perform faster memory accesses than otherwise. This patch adds support for alignment hints in the assembler and disassembler, and fills in known alignment during codegen. llvm-svn: 363806
691 lines
22 KiB
C++
691 lines
22 KiB
C++
//===-- SystemZAsmPrinter.cpp - SystemZ LLVM assembly printer -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Streams SystemZ assembly language and associated data, in the form of
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// MCInsts and MCExprs respectively.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZAsmPrinter.h"
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#include "MCTargetDesc/SystemZInstPrinter.h"
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#include "SystemZConstantPoolValue.h"
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#include "SystemZMCInstLower.h"
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#include "TargetInfo/SystemZTargetInfo.h"
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/IR/Mangler.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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// Return an RI instruction like MI with opcode Opcode, but with the
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// GR64 register operands turned into GR32s.
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static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) {
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if (MI->isCompare())
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return MCInstBuilder(Opcode)
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.addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
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.addImm(MI->getOperand(1).getImm());
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else
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return MCInstBuilder(Opcode)
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.addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
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.addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
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.addImm(MI->getOperand(2).getImm());
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}
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// Return an RI instruction like MI with opcode Opcode, but with the
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// GR64 register operands turned into GRH32s.
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static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) {
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if (MI->isCompare())
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return MCInstBuilder(Opcode)
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.addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
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.addImm(MI->getOperand(1).getImm());
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else
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return MCInstBuilder(Opcode)
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.addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
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.addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
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.addImm(MI->getOperand(2).getImm());
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}
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// Return an RI instruction like MI with opcode Opcode, but with the
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// R2 register turned into a GR64.
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static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) {
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return MCInstBuilder(Opcode)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()))
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.addImm(MI->getOperand(3).getImm())
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.addImm(MI->getOperand(4).getImm())
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.addImm(MI->getOperand(5).getImm());
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}
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static const MCSymbolRefExpr *getTLSGetOffset(MCContext &Context) {
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StringRef Name = "__tls_get_offset";
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return MCSymbolRefExpr::create(Context.getOrCreateSymbol(Name),
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MCSymbolRefExpr::VK_PLT,
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Context);
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}
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static const MCSymbolRefExpr *getGlobalOffsetTable(MCContext &Context) {
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StringRef Name = "_GLOBAL_OFFSET_TABLE_";
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return MCSymbolRefExpr::create(Context.getOrCreateSymbol(Name),
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MCSymbolRefExpr::VK_None,
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Context);
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}
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// MI is an instruction that accepts an optional alignment hint,
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// and which was already lowered to LoweredMI. If the alignment
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// of the original memory operand is known, update LoweredMI to
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// an instruction with the corresponding hint set.
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static void lowerAlignmentHint(const MachineInstr *MI, MCInst &LoweredMI,
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unsigned Opcode) {
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if (!MI->hasOneMemOperand())
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return;
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const MachineMemOperand *MMO = *MI->memoperands_begin();
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unsigned AlignmentHint = 0;
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if (MMO->getAlignment() >= 16)
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AlignmentHint = 4;
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else if (MMO->getAlignment() >= 8)
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AlignmentHint = 3;
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if (AlignmentHint == 0)
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return;
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LoweredMI.setOpcode(Opcode);
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LoweredMI.addOperand(MCOperand::createImm(AlignmentHint));
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}
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// MI loads the high part of a vector from memory. Return an instruction
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// that uses replicating vector load Opcode to do the same thing.
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static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode) {
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return MCInstBuilder(Opcode)
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.addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(MI->getOperand(3).getReg());
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}
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// MI stores the high part of a vector to memory. Return an instruction
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// that uses elemental vector store Opcode to do the same thing.
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static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) {
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return MCInstBuilder(Opcode)
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.addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(MI->getOperand(3).getReg())
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.addImm(0);
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}
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void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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SystemZMCInstLower Lower(MF->getContext(), *this);
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MCInst LoweredMI;
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switch (MI->getOpcode()) {
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case SystemZ::Return:
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LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D);
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break;
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case SystemZ::CondReturn:
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LoweredMI = MCInstBuilder(SystemZ::BCR)
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.addImm(MI->getOperand(0).getImm())
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.addImm(MI->getOperand(1).getImm())
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.addReg(SystemZ::R14D);
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break;
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case SystemZ::CRBReturn:
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LoweredMI = MCInstBuilder(SystemZ::CRB)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R14D)
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.addImm(0);
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break;
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case SystemZ::CGRBReturn:
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LoweredMI = MCInstBuilder(SystemZ::CGRB)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R14D)
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.addImm(0);
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break;
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case SystemZ::CIBReturn:
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LoweredMI = MCInstBuilder(SystemZ::CIB)
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.addReg(MI->getOperand(0).getReg())
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.addImm(MI->getOperand(1).getImm())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R14D)
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.addImm(0);
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break;
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case SystemZ::CGIBReturn:
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LoweredMI = MCInstBuilder(SystemZ::CGIB)
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.addReg(MI->getOperand(0).getReg())
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.addImm(MI->getOperand(1).getImm())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R14D)
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.addImm(0);
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break;
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case SystemZ::CLRBReturn:
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LoweredMI = MCInstBuilder(SystemZ::CLRB)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R14D)
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.addImm(0);
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break;
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case SystemZ::CLGRBReturn:
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LoweredMI = MCInstBuilder(SystemZ::CLGRB)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R14D)
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.addImm(0);
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break;
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case SystemZ::CLIBReturn:
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LoweredMI = MCInstBuilder(SystemZ::CLIB)
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.addReg(MI->getOperand(0).getReg())
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.addImm(MI->getOperand(1).getImm())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R14D)
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.addImm(0);
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break;
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case SystemZ::CLGIBReturn:
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LoweredMI = MCInstBuilder(SystemZ::CLGIB)
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.addReg(MI->getOperand(0).getReg())
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.addImm(MI->getOperand(1).getImm())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R14D)
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.addImm(0);
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break;
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case SystemZ::CallBRASL:
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LoweredMI = MCInstBuilder(SystemZ::BRASL)
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.addReg(SystemZ::R14D)
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.addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));
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break;
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case SystemZ::CallBASR:
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LoweredMI = MCInstBuilder(SystemZ::BASR)
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.addReg(SystemZ::R14D)
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.addReg(MI->getOperand(0).getReg());
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break;
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case SystemZ::CallJG:
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LoweredMI = MCInstBuilder(SystemZ::JG)
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.addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));
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break;
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case SystemZ::CallBRCL:
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LoweredMI = MCInstBuilder(SystemZ::BRCL)
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.addImm(MI->getOperand(0).getImm())
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.addImm(MI->getOperand(1).getImm())
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.addExpr(Lower.getExpr(MI->getOperand(2), MCSymbolRefExpr::VK_PLT));
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break;
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case SystemZ::CallBR:
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LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R1D);
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break;
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case SystemZ::CallBCR:
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LoweredMI = MCInstBuilder(SystemZ::BCR)
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.addImm(MI->getOperand(0).getImm())
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.addImm(MI->getOperand(1).getImm())
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.addReg(SystemZ::R1D);
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break;
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case SystemZ::CRBCall:
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LoweredMI = MCInstBuilder(SystemZ::CRB)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addImm(0);
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break;
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case SystemZ::CGRBCall:
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LoweredMI = MCInstBuilder(SystemZ::CGRB)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addImm(0);
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break;
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case SystemZ::CIBCall:
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LoweredMI = MCInstBuilder(SystemZ::CIB)
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.addReg(MI->getOperand(0).getReg())
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.addImm(MI->getOperand(1).getImm())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addImm(0);
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break;
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case SystemZ::CGIBCall:
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LoweredMI = MCInstBuilder(SystemZ::CGIB)
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.addReg(MI->getOperand(0).getReg())
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.addImm(MI->getOperand(1).getImm())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addImm(0);
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break;
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case SystemZ::CLRBCall:
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LoweredMI = MCInstBuilder(SystemZ::CLRB)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addImm(0);
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break;
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case SystemZ::CLGRBCall:
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LoweredMI = MCInstBuilder(SystemZ::CLGRB)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addImm(0);
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break;
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case SystemZ::CLIBCall:
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LoweredMI = MCInstBuilder(SystemZ::CLIB)
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.addReg(MI->getOperand(0).getReg())
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.addImm(MI->getOperand(1).getImm())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addImm(0);
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break;
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case SystemZ::CLGIBCall:
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LoweredMI = MCInstBuilder(SystemZ::CLGIB)
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.addReg(MI->getOperand(0).getReg())
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.addImm(MI->getOperand(1).getImm())
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.addImm(MI->getOperand(2).getImm())
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.addReg(SystemZ::R1D)
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.addImm(0);
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break;
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case SystemZ::TLS_GDCALL:
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LoweredMI = MCInstBuilder(SystemZ::BRASL)
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.addReg(SystemZ::R14D)
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.addExpr(getTLSGetOffset(MF->getContext()))
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.addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_TLSGD));
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break;
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case SystemZ::TLS_LDCALL:
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LoweredMI = MCInstBuilder(SystemZ::BRASL)
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.addReg(SystemZ::R14D)
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.addExpr(getTLSGetOffset(MF->getContext()))
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.addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_TLSLDM));
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break;
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case SystemZ::GOT:
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LoweredMI = MCInstBuilder(SystemZ::LARL)
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.addReg(MI->getOperand(0).getReg())
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.addExpr(getGlobalOffsetTable(MF->getContext()));
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break;
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case SystemZ::IILF64:
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LoweredMI = MCInstBuilder(SystemZ::IILF)
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.addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
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.addImm(MI->getOperand(2).getImm());
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break;
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case SystemZ::IIHF64:
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LoweredMI = MCInstBuilder(SystemZ::IIHF)
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.addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
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.addImm(MI->getOperand(2).getImm());
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break;
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case SystemZ::RISBHH:
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case SystemZ::RISBHL:
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LoweredMI = lowerRIEfLow(MI, SystemZ::RISBHG);
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break;
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case SystemZ::RISBLH:
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case SystemZ::RISBLL:
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LoweredMI = lowerRIEfLow(MI, SystemZ::RISBLG);
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break;
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case SystemZ::VLVGP32:
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LoweredMI = MCInstBuilder(SystemZ::VLVGP)
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.addReg(MI->getOperand(0).getReg())
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.addReg(SystemZMC::getRegAsGR64(MI->getOperand(1).getReg()))
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.addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()));
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break;
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case SystemZ::VLR32:
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case SystemZ::VLR64:
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LoweredMI = MCInstBuilder(SystemZ::VLR)
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.addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
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.addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()));
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break;
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case SystemZ::VL:
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Lower.lower(MI, LoweredMI);
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lowerAlignmentHint(MI, LoweredMI, SystemZ::VLAlign);
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break;
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case SystemZ::VST:
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Lower.lower(MI, LoweredMI);
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lowerAlignmentHint(MI, LoweredMI, SystemZ::VSTAlign);
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break;
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case SystemZ::VLM:
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Lower.lower(MI, LoweredMI);
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lowerAlignmentHint(MI, LoweredMI, SystemZ::VLMAlign);
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break;
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case SystemZ::VSTM:
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Lower.lower(MI, LoweredMI);
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lowerAlignmentHint(MI, LoweredMI, SystemZ::VSTMAlign);
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break;
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case SystemZ::VL32:
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LoweredMI = lowerSubvectorLoad(MI, SystemZ::VLREPF);
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break;
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case SystemZ::VL64:
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LoweredMI = lowerSubvectorLoad(MI, SystemZ::VLREPG);
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break;
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case SystemZ::VST32:
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LoweredMI = lowerSubvectorStore(MI, SystemZ::VSTEF);
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break;
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case SystemZ::VST64:
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LoweredMI = lowerSubvectorStore(MI, SystemZ::VSTEG);
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break;
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case SystemZ::LFER:
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LoweredMI = MCInstBuilder(SystemZ::VLGVF)
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.addReg(SystemZMC::getRegAsGR64(MI->getOperand(0).getReg()))
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.addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()))
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.addReg(0).addImm(0);
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break;
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case SystemZ::LEFR:
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LoweredMI = MCInstBuilder(SystemZ::VLVGF)
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.addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
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.addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
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.addReg(MI->getOperand(1).getReg())
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.addReg(0).addImm(0);
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break;
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#define LOWER_LOW(NAME) \
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case SystemZ::NAME##64: LoweredMI = lowerRILow(MI, SystemZ::NAME); break
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LOWER_LOW(IILL);
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LOWER_LOW(IILH);
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LOWER_LOW(TMLL);
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LOWER_LOW(TMLH);
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LOWER_LOW(NILL);
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LOWER_LOW(NILH);
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LOWER_LOW(NILF);
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LOWER_LOW(OILL);
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LOWER_LOW(OILH);
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LOWER_LOW(OILF);
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LOWER_LOW(XILF);
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#undef LOWER_LOW
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#define LOWER_HIGH(NAME) \
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case SystemZ::NAME##64: LoweredMI = lowerRIHigh(MI, SystemZ::NAME); break
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LOWER_HIGH(IIHL);
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LOWER_HIGH(IIHH);
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LOWER_HIGH(TMHL);
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LOWER_HIGH(TMHH);
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LOWER_HIGH(NIHL);
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LOWER_HIGH(NIHH);
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LOWER_HIGH(NIHF);
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LOWER_HIGH(OIHL);
|
|
LOWER_HIGH(OIHH);
|
|
LOWER_HIGH(OIHF);
|
|
LOWER_HIGH(XIHF);
|
|
|
|
#undef LOWER_HIGH
|
|
|
|
case SystemZ::Serialize:
|
|
if (MF->getSubtarget<SystemZSubtarget>().hasFastSerialization())
|
|
LoweredMI = MCInstBuilder(SystemZ::BCRAsm)
|
|
.addImm(14).addReg(SystemZ::R0D);
|
|
else
|
|
LoweredMI = MCInstBuilder(SystemZ::BCRAsm)
|
|
.addImm(15).addReg(SystemZ::R0D);
|
|
break;
|
|
|
|
// Emit nothing here but a comment if we can.
|
|
case SystemZ::MemBarrier:
|
|
OutStreamer->emitRawComment("MEMBARRIER");
|
|
return;
|
|
|
|
// We want to emit "j .+2" for traps, jumping to the relative immediate field
|
|
// of the jump instruction, which is an illegal instruction. We cannot emit a
|
|
// "." symbol, so create and emit a temp label before the instruction and use
|
|
// that instead.
|
|
case SystemZ::Trap: {
|
|
MCSymbol *DotSym = OutContext.createTempSymbol();
|
|
OutStreamer->EmitLabel(DotSym);
|
|
|
|
const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(DotSym, OutContext);
|
|
const MCConstantExpr *ConstExpr = MCConstantExpr::create(2, OutContext);
|
|
LoweredMI = MCInstBuilder(SystemZ::J)
|
|
.addExpr(MCBinaryExpr::createAdd(Expr, ConstExpr, OutContext));
|
|
}
|
|
break;
|
|
|
|
// Conditional traps will create a branch on condition instruction that jumps
|
|
// to the relative immediate field of the jump instruction. (eg. "jo .+2")
|
|
case SystemZ::CondTrap: {
|
|
MCSymbol *DotSym = OutContext.createTempSymbol();
|
|
OutStreamer->EmitLabel(DotSym);
|
|
|
|
const MCSymbolRefExpr *Expr = MCSymbolRefExpr::create(DotSym, OutContext);
|
|
const MCConstantExpr *ConstExpr = MCConstantExpr::create(2, OutContext);
|
|
LoweredMI = MCInstBuilder(SystemZ::BRC)
|
|
.addImm(MI->getOperand(0).getImm())
|
|
.addImm(MI->getOperand(1).getImm())
|
|
.addExpr(MCBinaryExpr::createAdd(Expr, ConstExpr, OutContext));
|
|
}
|
|
break;
|
|
|
|
case TargetOpcode::STACKMAP:
|
|
LowerSTACKMAP(*MI);
|
|
return;
|
|
|
|
case TargetOpcode::PATCHPOINT:
|
|
LowerPATCHPOINT(*MI, Lower);
|
|
return;
|
|
|
|
default:
|
|
Lower.lower(MI, LoweredMI);
|
|
break;
|
|
}
|
|
EmitToStreamer(*OutStreamer, LoweredMI);
|
|
}
|
|
|
|
|
|
// Emit the largest nop instruction smaller than or equal to NumBytes
|
|
// bytes. Return the size of nop emitted.
|
|
static unsigned EmitNop(MCContext &OutContext, MCStreamer &OutStreamer,
|
|
unsigned NumBytes, const MCSubtargetInfo &STI) {
|
|
if (NumBytes < 2) {
|
|
llvm_unreachable("Zero nops?");
|
|
return 0;
|
|
}
|
|
else if (NumBytes < 4) {
|
|
OutStreamer.EmitInstruction(MCInstBuilder(SystemZ::BCRAsm)
|
|
.addImm(0).addReg(SystemZ::R0D), STI);
|
|
return 2;
|
|
}
|
|
else if (NumBytes < 6) {
|
|
OutStreamer.EmitInstruction(MCInstBuilder(SystemZ::BCAsm)
|
|
.addImm(0).addReg(0).addImm(0).addReg(0),
|
|
STI);
|
|
return 4;
|
|
}
|
|
else {
|
|
MCSymbol *DotSym = OutContext.createTempSymbol();
|
|
const MCSymbolRefExpr *Dot = MCSymbolRefExpr::create(DotSym, OutContext);
|
|
OutStreamer.EmitInstruction(MCInstBuilder(SystemZ::BRCLAsm)
|
|
.addImm(0).addExpr(Dot), STI);
|
|
OutStreamer.EmitLabel(DotSym);
|
|
return 6;
|
|
}
|
|
}
|
|
|
|
void SystemZAsmPrinter::LowerSTACKMAP(const MachineInstr &MI) {
|
|
const SystemZInstrInfo *TII =
|
|
static_cast<const SystemZInstrInfo *>(MF->getSubtarget().getInstrInfo());
|
|
|
|
unsigned NumNOPBytes = MI.getOperand(1).getImm();
|
|
|
|
SM.recordStackMap(MI);
|
|
assert(NumNOPBytes % 2 == 0 && "Invalid number of NOP bytes requested!");
|
|
|
|
// Scan ahead to trim the shadow.
|
|
unsigned ShadowBytes = 0;
|
|
const MachineBasicBlock &MBB = *MI.getParent();
|
|
MachineBasicBlock::const_iterator MII(MI);
|
|
++MII;
|
|
while (ShadowBytes < NumNOPBytes) {
|
|
if (MII == MBB.end() ||
|
|
MII->getOpcode() == TargetOpcode::PATCHPOINT ||
|
|
MII->getOpcode() == TargetOpcode::STACKMAP)
|
|
break;
|
|
ShadowBytes += TII->getInstSizeInBytes(*MII);
|
|
if (MII->isCall())
|
|
break;
|
|
++MII;
|
|
}
|
|
|
|
// Emit nops.
|
|
while (ShadowBytes < NumNOPBytes)
|
|
ShadowBytes += EmitNop(OutContext, *OutStreamer, NumNOPBytes - ShadowBytes,
|
|
getSubtargetInfo());
|
|
}
|
|
|
|
// Lower a patchpoint of the form:
|
|
// [<def>], <id>, <numBytes>, <target>, <numArgs>
|
|
void SystemZAsmPrinter::LowerPATCHPOINT(const MachineInstr &MI,
|
|
SystemZMCInstLower &Lower) {
|
|
SM.recordPatchPoint(MI);
|
|
PatchPointOpers Opers(&MI);
|
|
|
|
unsigned EncodedBytes = 0;
|
|
const MachineOperand &CalleeMO = Opers.getCallTarget();
|
|
|
|
if (CalleeMO.isImm()) {
|
|
uint64_t CallTarget = CalleeMO.getImm();
|
|
if (CallTarget) {
|
|
unsigned ScratchIdx = -1;
|
|
unsigned ScratchReg = 0;
|
|
do {
|
|
ScratchIdx = Opers.getNextScratchIdx(ScratchIdx + 1);
|
|
ScratchReg = MI.getOperand(ScratchIdx).getReg();
|
|
} while (ScratchReg == SystemZ::R0D);
|
|
|
|
// Materialize the call target address
|
|
EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::LLILF)
|
|
.addReg(ScratchReg)
|
|
.addImm(CallTarget & 0xFFFFFFFF));
|
|
EncodedBytes += 6;
|
|
if (CallTarget >> 32) {
|
|
EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::IIHF)
|
|
.addReg(ScratchReg)
|
|
.addImm(CallTarget >> 32));
|
|
EncodedBytes += 6;
|
|
}
|
|
|
|
EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::BASR)
|
|
.addReg(SystemZ::R14D)
|
|
.addReg(ScratchReg));
|
|
EncodedBytes += 2;
|
|
}
|
|
} else if (CalleeMO.isGlobal()) {
|
|
const MCExpr *Expr = Lower.getExpr(CalleeMO, MCSymbolRefExpr::VK_PLT);
|
|
EmitToStreamer(*OutStreamer, MCInstBuilder(SystemZ::BRASL)
|
|
.addReg(SystemZ::R14D)
|
|
.addExpr(Expr));
|
|
EncodedBytes += 6;
|
|
}
|
|
|
|
// Emit padding.
|
|
unsigned NumBytes = Opers.getNumPatchBytes();
|
|
assert(NumBytes >= EncodedBytes &&
|
|
"Patchpoint can't request size less than the length of a call.");
|
|
assert((NumBytes - EncodedBytes) % 2 == 0 &&
|
|
"Invalid number of NOP bytes requested!");
|
|
while (EncodedBytes < NumBytes)
|
|
EncodedBytes += EmitNop(OutContext, *OutStreamer, NumBytes - EncodedBytes,
|
|
getSubtargetInfo());
|
|
}
|
|
|
|
// Convert a SystemZ-specific constant pool modifier into the associated
|
|
// MCSymbolRefExpr variant kind.
|
|
static MCSymbolRefExpr::VariantKind
|
|
getModifierVariantKind(SystemZCP::SystemZCPModifier Modifier) {
|
|
switch (Modifier) {
|
|
case SystemZCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
|
|
case SystemZCP::TLSLDM: return MCSymbolRefExpr::VK_TLSLDM;
|
|
case SystemZCP::DTPOFF: return MCSymbolRefExpr::VK_DTPOFF;
|
|
case SystemZCP::NTPOFF: return MCSymbolRefExpr::VK_NTPOFF;
|
|
}
|
|
llvm_unreachable("Invalid SystemCPModifier!");
|
|
}
|
|
|
|
void SystemZAsmPrinter::
|
|
EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
|
|
auto *ZCPV = static_cast<SystemZConstantPoolValue*>(MCPV);
|
|
|
|
const MCExpr *Expr =
|
|
MCSymbolRefExpr::create(getSymbol(ZCPV->getGlobalValue()),
|
|
getModifierVariantKind(ZCPV->getModifier()),
|
|
OutContext);
|
|
uint64_t Size = getDataLayout().getTypeAllocSize(ZCPV->getType());
|
|
|
|
OutStreamer->EmitValue(Expr, Size);
|
|
}
|
|
|
|
bool SystemZAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
|
|
const char *ExtraCode,
|
|
raw_ostream &OS) {
|
|
if (ExtraCode)
|
|
return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
|
|
SystemZMCInstLower Lower(MF->getContext(), *this);
|
|
MCOperand MO(Lower.lowerOperand(MI->getOperand(OpNo)));
|
|
SystemZInstPrinter::printOperand(MO, MAI, OS);
|
|
return false;
|
|
}
|
|
|
|
bool SystemZAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
|
|
unsigned OpNo,
|
|
const char *ExtraCode,
|
|
raw_ostream &OS) {
|
|
SystemZInstPrinter::printAddress(MI->getOperand(OpNo).getReg(),
|
|
MI->getOperand(OpNo + 1).getImm(),
|
|
MI->getOperand(OpNo + 2).getReg(), OS);
|
|
return false;
|
|
}
|
|
|
|
void SystemZAsmPrinter::EmitEndOfAsmFile(Module &M) {
|
|
emitStackMaps(SM);
|
|
}
|
|
|
|
// Force static initialization.
|
|
extern "C" void LLVMInitializeSystemZAsmPrinter() {
|
|
RegisterAsmPrinter<SystemZAsmPrinter> X(getTheSystemZTarget());
|
|
}
|