David Green df614e3ecd [ARM] Expand the range of allowed post-incs in load/store optimizer ... Currently the load/store optimizer will only fold in increments of the same size as the load/store. This patch expands that to any legal immediate for the post-inc instruction. Differential Revision: https://reviews.llvm.org/D95885		2021-02-18 14:59:02 +00:00
..
AArch64	[SVE][CodeGen] Expand SVE MULH[SU] and [SU]MUL_LOHI nodes	2021-02-18 10:06:24 +00:00
AMDGPU	[AMDGPU] Tidy up a FIXME fixed by D34973	2021-02-18 14:28:27 +00:00
ARC
ARM	[ARM] Expand the range of allowed post-incs in load/store optimizer	2021-02-18 14:59:02 +00:00
AVR	[AVR] Fix a bug in 16-bit shifts	2021-02-14 11:54:55 +08:00
BPF
Generic	[CodeGen] New pass: Replace vector intrinsics with call to vector library	2021-02-12 12:53:27 -05:00
Hexagon
Inputs
Lanai
Mips
MIR	[AMDGPU] gfx90a support	2021-02-17 16:01:32 -08:00
MSP430
NVPTX
PowerPC	[PowerPC] Exploit the vinsw, vinsd, and vins[wd][lr]x instructions on P10	2021-02-18 14:17:47 +00:00
RISCV	[RISCV] Begin to support more subvector inserts/extracts	2021-02-18 10:18:27 +00:00
SPARC
SystemZ	[SystemZ] Separate LoZ ELF specifics in tablegen.	2021-02-17 16:11:58 -05:00
Thumb
Thumb2	[ARM] Expand the range of allowed post-incs in load/store optimizer	2021-02-18 14:59:02 +00:00
VE
WebAssembly	[WebAssemblly] Fix EHPadStack update in fixCallUnwindMismatches	2021-02-17 12:14:11 -08:00
WinCFGuard
WinEH
X86	[X86][SSE] Add uniform vector shift test coverage for (sra (trunc (sr[al] x, c1)), c2) folds	2021-02-18 11:38:41 +00:00
XCore