mirror of
https://github.com/RPCS3/llvm-mirror.git
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0773b05cfa
This changes the definition of t2DoLoopStart from
t2DoLoopStart rGPR
to
GPRlr = t2DoLoopStart rGPR
This will hopefully mean that low overhead loops are more tied together,
and we can more reliably generate loops without reverting or being at
the whims of the register allocator.
This is a fairly simple change in itself, but leads to a number of other
required alterations.
- The hardware loop pass, if UsePhi is set, now generates loops of the
form:
%start = llvm.start.loop.iterations(%N)
loop:
%p = phi [%start], [%dec]
%dec = llvm.loop.decrement.reg(%p, 1)
%c = icmp ne %dec, 0
br %c, loop, exit
- For this a new llvm.start.loop.iterations intrinsic was added, identical
to llvm.set.loop.iterations but produces a value as seen above, gluing
the loop together more through def-use chains.
- This new instrinsic conceptually produces the same output as input,
which is taught to SCEV so that the checks in MVETailPredication are not
affected.
- Some minor changes are needed to the ARMLowOverheadLoop pass, but it has
been left mostly as before. We should now more reliably be able to tell
that the t2DoLoopStart is correct without having to prove it, but
t2WhileLoopStart and tail-predicated loops will remain the same.
- And all the tests have been updated. There are a lot of them!
This patch on it's own might cause more trouble that it helps, with more
tail-predicated loops being reverted, but some additional patches can
hopefully improve upon that to get to something that is better overall.
Differential Revision: https://reviews.llvm.org/D89881
157 lines
7.6 KiB
YAML
157 lines
7.6 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
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--- |
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define dso_local <4 x i32> @invariant_predicated_add_use(i16* nocapture readonly %a, i32* %c, i32 %N, <4 x i32> %pass) #0 {
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entry:
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%cmp9 = icmp eq i32 %N, 0
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%tmp = add i32 %N, 3
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%tmp1 = lshr i32 %tmp, 2
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%tmp2 = shl nuw i32 %tmp1, 2
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%tmp3 = add i32 %tmp2, -4
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%tmp4 = lshr i32 %tmp3, 2
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%tmp5 = add nuw nsw i32 %tmp4, 1
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br i1 %cmp9, label %exit, label %vector.ph
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vector.ph: ; preds = %entry
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%start = call i32 @llvm.start.loop.iterations.i32(i32 %tmp5)
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%lsr.iv1 = phi i32 [ %lsr.iv.next, %vector.body ], [ %start, %vector.ph ]
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%lsr.iv = phi i16* [ %scevgep, %vector.body ], [ %a, %vector.ph ]
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%tmp7 = phi i32 [ %N, %vector.ph ], [ %tmp9, %vector.body ]
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%lsr.iv17 = bitcast i16* %lsr.iv to <4 x i16>*
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%tmp8 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %tmp7)
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%tmp9 = sub i32 %tmp7, 4
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%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv17, i32 2, <4 x i1> %tmp8, <4 x i16> undef)
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%tmp10 = sext <4 x i16> %wide.masked.load to <4 x i32>
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%acc.next = tail call <4 x i32> @llvm.arm.mve.add.predicated.v4i32.v4i1(<4 x i32> %pass, <4 x i32> %tmp10, <4 x i1> %tmp8, <4 x i32> undef)
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%scevgep = getelementptr i16, i16* %lsr.iv, i32 4
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%tmp11 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %lsr.iv1, i32 1)
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%tmp12 = icmp ne i32 %tmp11, 0
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%lsr.iv.next = add nsw i32 %lsr.iv1, -1
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br i1 %tmp12, label %vector.body, label %exit
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exit: ; preds = %vector.body, %entry
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%res = phi <4 x i32> [ zeroinitializer, %entry ], [ %acc.next, %vector.body ]
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ret <4 x i32> %res
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}
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declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>)
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declare i32 @llvm.start.loop.iterations.i32(i32)
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32)
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declare <4 x i1> @llvm.arm.mve.vctp32(i32)
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declare <4 x i32> @llvm.arm.mve.add.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)
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...
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---
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name: invariant_predicated_add_use
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alignment: 2
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tracksRegLiveness: true
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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frameInfo:
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stackSize: 8
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offsetAdjustment: 0
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maxAlignment: 8
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fixedStack:
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- { id: 0, type: default, offset: 0, size: 16, alignment: 8, stack-id: default,
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isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: invariant_predicated_add_use
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.3(0x30000000), %bb.1(0x50000000)
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; CHECK: liveins: $lr, $r0, $r2, $r7
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; CHECK: frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
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; CHECK: tCBZ $r2, %bb.3
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; CHECK: bb.1.vector.ph:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: liveins: $r0, $r2
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; CHECK: renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
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; CHECK: renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8)
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; CHECK: $lr = MVE_DLSTP_32 killed renamable $r2
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; CHECK: bb.2.vector.body:
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; CHECK: successors: %bb.2(0x7c000000), %bb.4(0x04000000)
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; CHECK: liveins: $lr, $q0, $r0
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; CHECK: renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 0, $noreg :: (load 8 from %ir.lsr.iv17, align 2)
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; CHECK: renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 0, killed $noreg, undef renamable $q1
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; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.2
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; CHECK: tB %bb.4, 14 /* CC::al */, $noreg
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; CHECK: bb.3:
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; CHECK: successors: %bb.4(0x80000000)
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; CHECK: renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
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; CHECK: bb.4.exit:
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; CHECK: liveins: $q1
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; CHECK: renamable $r0, renamable $r1 = VMOVRRD renamable $d2, 14 /* CC::al */, $noreg
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; CHECK: renamable $r2, renamable $r3 = VMOVRRD killed renamable $d3, 14 /* CC::al */, $noreg, implicit killed $q1
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; CHECK: tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3
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bb.0.entry:
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successors: %bb.3(0x30000000), %bb.1(0x50000000)
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liveins: $r0, $r2, $r7, $lr
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frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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tCBZ $r2, %bb.3
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bb.1.vector.ph:
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successors: %bb.2(0x80000000)
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liveins: $r0, $r2
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renamable $r1, dead $cpsr = tADDi3 renamable $r2, 3, 14 /* CC::al */, $noreg
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renamable $r3, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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renamable $r1 = t2BICri killed renamable $r1, 3, 14 /* CC::al */, $noreg, $noreg
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renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14 /* CC::al */, $noreg
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renamable $r3 = nuw nsw t2ADDrs killed renamable $r3, killed renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg
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renamable $r1 = tADDrSPi $sp, 2, 14 /* CC::al */, $noreg
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renamable $q0 = MVE_VLDRWU32 killed renamable $r1, 0, 0, $noreg :: (load 16 from %fixed-stack.0, align 8)
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$lr = t2DoLoopStart renamable $r3
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$r1 = tMOVr killed $r3, 14 /* CC::al */, $noreg
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bb.2.vector.body:
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successors: %bb.2(0x7c000000), %bb.4(0x04000000)
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liveins: $q0, $r0, $r1, $r2
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renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg
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$lr = tMOVr $r1, 14 /* CC::al */, $noreg
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renamable $r1, dead $cpsr = nsw tSUBi8 killed $r1, 1, 14 /* CC::al */, $noreg
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renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
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renamable $lr = t2LoopDec killed renamable $lr, 1
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MVE_VPST 4, implicit $vpr
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renamable $r0, renamable $q1 = MVE_VLDRHS32_post killed renamable $r0, 8, 1, renamable $vpr :: (load 8 from %ir.lsr.iv17, align 2)
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renamable $q1 = MVE_VADDi32 renamable $q0, killed renamable $q1, 1, killed renamable $vpr, undef renamable $q1
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t2LoopEnd killed renamable $lr, %bb.2, implicit-def dead $cpsr
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tB %bb.4, 14 /* CC::al */, $noreg
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bb.3:
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successors: %bb.4(0x80000000)
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renamable $q1 = MVE_VMOVimmi32 0, 0, $noreg, undef renamable $q1
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bb.4.exit:
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liveins: $q1
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renamable $r0, renamable $r1 = VMOVRRD renamable $d2, 14 /* CC::al */, $noreg
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renamable $r2, renamable $r3 = VMOVRRD killed renamable $d3, 14 /* CC::al */, $noreg, implicit $q1
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tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0, implicit killed $r1, implicit killed $r2, implicit killed $r3
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...
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