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https://github.com/RPCS3/llvm-mirror.git
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9ee7075ca5
MVE has a dual lane vector move instruction, capable of moving two general purpose registers into lanes of a vector register. They look like one of: vmov q0[2], q0[0], r2, r0 vmov q0[3], q0[1], r3, r1 They only accept these lane indices though (and only insert into an i32), either moving lanes 1 and 3, or 0 and 2. This patch adds some tablegen patterns for them, selecting from vector inserts elements. Because the insert_elements are know to be canonicalized to ascending order there are several patterns that we need to select. These lane indices are: 3 2 1 0 -> vmovqrr 31; vmovqrr 20 3 2 1 -> vmovqrr 31; vmov 2 3 1 -> vmovqrr 31 2 1 0 -> vmovqrr 20; vmov 1 2 0 -> vmovqrr 20 With the top one being the most common. All other potential patterns of lane indices will be matched by a combination of these and the individual vmov pattern already present. This does mean that we are selecting several machine instructions at once due to the need to re-arrange the inserts, but in this case there is nothing else that will attempt to match an insert_vector_elt node. This is a recommit of 6cc3d80a84884a79967fffa4596c14001b8ba8a3 after fixing the backward instruction definitions.
64 lines
2.1 KiB
LLVM
64 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
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define arm_aapcs_vfpcc <16 x i8> @abs_v16i8(<16 x i8> %s1) {
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; CHECK-LABEL: abs_v16i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vabs.s8 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = icmp slt <16 x i8> %s1, zeroinitializer
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%1 = sub nsw <16 x i8> zeroinitializer, %s1
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%2 = select <16 x i1> %0, <16 x i8> %1, <16 x i8> %s1
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ret <16 x i8> %2
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}
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define arm_aapcs_vfpcc <8 x i16> @abs_v8i16(<8 x i16> %s1) {
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; CHECK-LABEL: abs_v8i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vabs.s16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = icmp slt <8 x i16> %s1, zeroinitializer
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%1 = sub nsw <8 x i16> zeroinitializer, %s1
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%2 = select <8 x i1> %0, <8 x i16> %1, <8 x i16> %s1
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ret <8 x i16> %2
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}
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define arm_aapcs_vfpcc <4 x i32> @abs_v4i32(<4 x i32> %s1) {
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; CHECK-LABEL: abs_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vabs.s32 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = icmp slt <4 x i32> %s1, zeroinitializer
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%1 = sub nsw <4 x i32> zeroinitializer, %s1
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%2 = select <4 x i1> %0, <4 x i32> %1, <4 x i32> %s1
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ret <4 x i32> %2
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}
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define arm_aapcs_vfpcc <2 x i64> @abs_v2i64(<2 x i64> %s1) {
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; CHECK-LABEL: abs_v2i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, s3
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; CHECK-NEXT: vmov r1, s2
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; CHECK-NEXT: vmov r3, s1
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; CHECK-NEXT: vmov r2, s0
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; CHECK-NEXT: adds.w r1, r1, r0, asr #31
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; CHECK-NEXT: adc.w r12, r0, r0, asr #31
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; CHECK-NEXT: eor.w r1, r1, r0, asr #31
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; CHECK-NEXT: adds.w r2, r2, r3, asr #31
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; CHECK-NEXT: eor.w r0, r12, r0, asr #31
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; CHECK-NEXT: eor.w r2, r2, r3, asr #31
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; CHECK-NEXT: vmov q0[2], q0[0], r2, r1
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; CHECK-NEXT: adc.w r1, r3, r3, asr #31
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; CHECK-NEXT: eor.w r1, r1, r3, asr #31
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; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = icmp slt <2 x i64> %s1, zeroinitializer
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%1 = sub nsw <2 x i64> zeroinitializer, %s1
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%2 = select <2 x i1> %0, <2 x i64> %1, <2 x i64> %s1
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ret <2 x i64> %2
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}
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