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9ee7075ca5
MVE has a dual lane vector move instruction, capable of moving two general purpose registers into lanes of a vector register. They look like one of: vmov q0[2], q0[0], r2, r0 vmov q0[3], q0[1], r3, r1 They only accept these lane indices though (and only insert into an i32), either moving lanes 1 and 3, or 0 and 2. This patch adds some tablegen patterns for them, selecting from vector inserts elements. Because the insert_elements are know to be canonicalized to ascending order there are several patterns that we need to select. These lane indices are: 3 2 1 0 -> vmovqrr 31; vmovqrr 20 3 2 1 -> vmovqrr 31; vmov 2 3 1 -> vmovqrr 31 2 1 0 -> vmovqrr 20; vmov 1 2 0 -> vmovqrr 20 With the top one being the most common. All other potential patterns of lane indices will be matched by a combination of these and the individual vmov pattern already present. This does mean that we are selecting several machine instructions at once due to the need to re-arrange the inserts, but in this case there is nothing else that will attempt to match an insert_vector_elt node. This is a recommit of 6cc3d80a84884a79967fffa4596c14001b8ba8a3 after fixing the backward instruction definitions.
91 lines
3.5 KiB
LLVM
91 lines
3.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -enable-arm-maskedgatscat=false %s -o 2>/dev/null - | FileCheck --check-prefix NOGATSCAT %s
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=-mve %s -o 2>/dev/null - | FileCheck --check-prefix NOMVE %s
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define arm_aapcs_vfpcc <4 x i32> @unscaled_i32_i32_gather(i8* %base, <4 x i32>* %offptr) {
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; NOGATSCAT-LABEL: unscaled_i32_i32_gather:
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; NOGATSCAT: @ %bb.0: @ %entry
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; NOGATSCAT-NEXT: vldrw.u32 q0, [r1]
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; NOGATSCAT-NEXT: vadd.i32 q0, q0, r0
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; NOGATSCAT-NEXT: vmov r0, s2
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; NOGATSCAT-NEXT: vmov r1, s0
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; NOGATSCAT-NEXT: vmov r2, s3
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; NOGATSCAT-NEXT: vmov r3, s1
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; NOGATSCAT-NEXT: ldr r0, [r0]
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; NOGATSCAT-NEXT: ldr r1, [r1]
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; NOGATSCAT-NEXT: ldr r2, [r2]
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; NOGATSCAT-NEXT: ldr r3, [r3]
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; NOGATSCAT-NEXT: vmov q0[2], q0[0], r1, r0
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; NOGATSCAT-NEXT: vmov q0[3], q0[1], r3, r2
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; NOGATSCAT-NEXT: bx lr
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;
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; NOMVE-LABEL: unscaled_i32_i32_gather:
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; NOMVE: @ %bb.0: @ %entry
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; NOMVE-NEXT: .save {r4, lr}
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; NOMVE-NEXT: push {r4, lr}
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; NOMVE-NEXT: ldm.w r1, {r2, r3, lr}
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; NOMVE-NEXT: ldr r4, [r1, #12]
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; NOMVE-NEXT: ldr.w r12, [r0, r2]
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; NOMVE-NEXT: ldr r1, [r0, r3]
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; NOMVE-NEXT: ldr.w r2, [r0, lr]
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; NOMVE-NEXT: ldr r3, [r0, r4]
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; NOMVE-NEXT: mov r0, r12
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; NOMVE-NEXT: pop {r4, pc}
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entry:
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%offs = load <4 x i32>, <4 x i32>* %offptr, align 4
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%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs
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%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i32*>
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%gather = call <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x i32> undef)
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ret <4 x i32> %gather
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}
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declare <4 x i32> @llvm.masked.gather.v4i32.v4p0i32(<4 x i32*>, i32, <4 x i1>, <4 x i32>)
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define arm_aapcs_vfpcc void @unscaled_i32_i8_scatter(i8* %base, <4 x i8>* %offptr, <4 x i32> %input) {
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; NOGATSCAT-LABEL: unscaled_i32_i8_scatter:
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; NOGATSCAT: @ %bb.0: @ %entry
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; NOGATSCAT-NEXT: vldrb.u32 q1, [r1]
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; NOGATSCAT-NEXT: vmov r1, s0
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; NOGATSCAT-NEXT: vadd.i32 q1, q1, r0
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; NOGATSCAT-NEXT: vmov r0, s4
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; NOGATSCAT-NEXT: str r1, [r0]
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; NOGATSCAT-NEXT: vmov r0, s5
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; NOGATSCAT-NEXT: vmov r1, s1
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; NOGATSCAT-NEXT: str r1, [r0]
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; NOGATSCAT-NEXT: vmov r0, s6
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; NOGATSCAT-NEXT: vmov r1, s2
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; NOGATSCAT-NEXT: str r1, [r0]
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; NOGATSCAT-NEXT: vmov r0, s7
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; NOGATSCAT-NEXT: vmov r1, s3
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; NOGATSCAT-NEXT: str r1, [r0]
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; NOGATSCAT-NEXT: bx lr
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;
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; NOMVE-LABEL: unscaled_i32_i8_scatter:
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; NOMVE: @ %bb.0: @ %entry
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; NOMVE-NEXT: .save {r4, lr}
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; NOMVE-NEXT: push {r4, lr}
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; NOMVE-NEXT: ldrb.w r12, [r1]
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; NOMVE-NEXT: ldrb.w lr, [r1, #1]
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; NOMVE-NEXT: ldrb r4, [r1, #2]
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; NOMVE-NEXT: ldrb r1, [r1, #3]
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; NOMVE-NEXT: str.w r2, [r0, r12]
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; NOMVE-NEXT: ldr r2, [sp, #8]
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; NOMVE-NEXT: str.w r3, [r0, lr]
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; NOMVE-NEXT: str r2, [r0, r4]
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; NOMVE-NEXT: ldr r2, [sp, #12]
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; NOMVE-NEXT: str r2, [r0, r1]
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; NOMVE-NEXT: pop {r4, pc}
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entry:
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%offs = load <4 x i8>, <4 x i8>* %offptr, align 1
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%offs.zext = zext <4 x i8> %offs to <4 x i32>
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%byte_ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs.zext
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%ptrs = bitcast <4 x i8*> %byte_ptrs to <4 x i32*>
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call void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32> %input, <4 x i32*> %ptrs, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 true>)
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ret void
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}
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declare void @llvm.masked.scatter.v4i32.v4p0i32(<4 x i32>, <4 x i32*>, i32, <4 x i1>)
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