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152 lines
5.1 KiB
LLVM
152 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -O0 -mattr=+mve %s -o - | FileCheck %s
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declare void @external_function()
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define arm_aapcs_vfpcc void @spill_vector_i32(<4 x i32> %v, <4 x i32>* %p) {
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; CHECK-LABEL: spill_vector_i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #40
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; CHECK-NEXT: sub sp, #40
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; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
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; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
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; CHECK-NEXT: bl external_function
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; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
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; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
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; CHECK-NEXT: vstrw.32 q0, [r0]
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; CHECK-NEXT: add sp, #40
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; CHECK-NEXT: pop {r7, pc}
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entry:
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call void @external_function()
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store <4 x i32> %v, <4 x i32>* %p, align 4
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ret void
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}
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define arm_aapcs_vfpcc void @spill_vector_i16(<8 x i16> %v, <8 x i16>* %p) {
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; CHECK-LABEL: spill_vector_i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #40
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; CHECK-NEXT: sub sp, #40
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; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
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; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
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; CHECK-NEXT: bl external_function
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; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
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; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
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; CHECK-NEXT: vstrh.16 q0, [r0]
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; CHECK-NEXT: add sp, #40
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; CHECK-NEXT: pop {r7, pc}
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entry:
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call void @external_function()
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store <8 x i16> %v, <8 x i16>* %p, align 2
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ret void
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}
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define arm_aapcs_vfpcc void @spill_vector_i8(<16 x i8> %v, <16 x i8>* %p) {
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; CHECK-LABEL: spill_vector_i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #40
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; CHECK-NEXT: sub sp, #40
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; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
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; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
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; CHECK-NEXT: bl external_function
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; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
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; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
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; CHECK-NEXT: vstrb.8 q0, [r0]
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; CHECK-NEXT: add sp, #40
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; CHECK-NEXT: pop {r7, pc}
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entry:
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call void @external_function()
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store <16 x i8> %v, <16 x i8>* %p, align 1
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ret void
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}
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define arm_aapcs_vfpcc void @spill_vector_i64(<2 x i64> %v, <2 x i64>* %p) {
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; CHECK-LABEL: spill_vector_i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #40
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; CHECK-NEXT: sub sp, #40
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; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
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; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
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; CHECK-NEXT: bl external_function
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; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
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; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
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; CHECK-NEXT: vstrw.32 q0, [r0]
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; CHECK-NEXT: add sp, #40
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; CHECK-NEXT: pop {r7, pc}
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entry:
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call void @external_function()
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store <2 x i64> %v, <2 x i64>* %p, align 8
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ret void
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}
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define arm_aapcs_vfpcc void @spill_vector_f32(<4 x float> %v, <4 x float>* %p) {
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; CHECK-LABEL: spill_vector_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #40
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; CHECK-NEXT: sub sp, #40
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; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
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; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
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; CHECK-NEXT: bl external_function
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; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
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; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
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; CHECK-NEXT: vstrw.32 q0, [r0]
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; CHECK-NEXT: add sp, #40
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; CHECK-NEXT: pop {r7, pc}
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entry:
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call void @external_function()
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store <4 x float> %v, <4 x float>* %p, align 8
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ret void
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}
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define arm_aapcs_vfpcc void @spill_vector_f16(<8 x half> %v, <8 x half>* %p) {
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; CHECK-LABEL: spill_vector_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #40
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; CHECK-NEXT: sub sp, #40
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; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
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; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
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; CHECK-NEXT: bl external_function
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; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
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; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
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; CHECK-NEXT: vstrw.32 q0, [r0]
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; CHECK-NEXT: add sp, #40
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; CHECK-NEXT: pop {r7, pc}
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entry:
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call void @external_function()
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store <8 x half> %v, <8 x half>* %p, align 8
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ret void
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}
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define arm_aapcs_vfpcc void @spill_vector_f64(<2 x double> %v, <2 x double>* %p) {
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; CHECK-LABEL: spill_vector_f64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r7, lr}
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: .pad #40
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; CHECK-NEXT: sub sp, #40
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; CHECK-NEXT: str r0, [sp, #12] @ 4-byte Spill
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; CHECK-NEXT: vstrw.32 q0, [sp, #16] @ 16-byte Spill
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; CHECK-NEXT: bl external_function
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; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
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; CHECK-NEXT: vldrw.u32 q0, [sp, #16] @ 16-byte Reload
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; CHECK-NEXT: vstrw.32 q0, [r0]
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; CHECK-NEXT: add sp, #40
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; CHECK-NEXT: pop {r7, pc}
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entry:
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call void @external_function()
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store <2 x double> %v, <2 x double>* %p, align 8
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ret void
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}
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