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https://github.com/RPCS3/llvm-mirror.git
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9ee7075ca5
MVE has a dual lane vector move instruction, capable of moving two general purpose registers into lanes of a vector register. They look like one of: vmov q0[2], q0[0], r2, r0 vmov q0[3], q0[1], r3, r1 They only accept these lane indices though (and only insert into an i32), either moving lanes 1 and 3, or 0 and 2. This patch adds some tablegen patterns for them, selecting from vector inserts elements. Because the insert_elements are know to be canonicalized to ascending order there are several patterns that we need to select. These lane indices are: 3 2 1 0 -> vmovqrr 31; vmovqrr 20 3 2 1 -> vmovqrr 31; vmov 2 3 1 -> vmovqrr 31 2 1 0 -> vmovqrr 20; vmov 1 2 0 -> vmovqrr 20 With the top one being the most common. All other potential patterns of lane indices will be matched by a combination of these and the individual vmov pattern already present. This does mean that we are selecting several machine instructions at once due to the need to re-arrange the inserts, but in this case there is nothing else that will attempt to match an insert_vector_elt node. This is a recommit of 6cc3d80a84884a79967fffa4596c14001b8ba8a3 after fixing the backward instruction definitions.
165 lines
6.1 KiB
LLVM
165 lines
6.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp,+fp64 -verify-machineinstrs %s -o - | FileCheck %s
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; i32
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define <8 x i32> *@vld2_v4i32(<8 x i32> *%src, <4 x i32> *%dst) {
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; CHECK-LABEL: vld2_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vld20.32 {q0, q1}, [r0]
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; CHECK-NEXT: vld21.32 {q0, q1}, [r0]!
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; CHECK-NEXT: vadd.i32 q0, q0, q1
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; CHECK-NEXT: vstrw.32 q0, [r1]
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; CHECK-NEXT: bx lr
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entry:
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%l1 = load <8 x i32>, <8 x i32>* %src, align 4
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%s1 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%s2 = shufflevector <8 x i32> %l1, <8 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%a = add <4 x i32> %s1, %s2
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store <4 x i32> %a, <4 x i32> *%dst
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%ret = getelementptr inbounds <8 x i32>, <8 x i32>* %src, i32 1
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ret <8 x i32> *%ret
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}
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; i16
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define <16 x i16> *@vld2_v8i16(<16 x i16> *%src, <8 x i16> *%dst) {
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; CHECK-LABEL: vld2_v8i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vld20.16 {q0, q1}, [r0]
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; CHECK-NEXT: vld21.16 {q0, q1}, [r0]!
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; CHECK-NEXT: vadd.i16 q0, q0, q1
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; CHECK-NEXT: vstrw.32 q0, [r1]
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; CHECK-NEXT: bx lr
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entry:
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%l1 = load <16 x i16>, <16 x i16>* %src, align 4
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%s1 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%s2 = shufflevector <16 x i16> %l1, <16 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%a = add <8 x i16> %s1, %s2
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store <8 x i16> %a, <8 x i16> *%dst
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%ret = getelementptr inbounds <16 x i16>, <16 x i16>* %src, i32 1
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ret <16 x i16> *%ret
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}
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; i8
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define <32 x i8> *@vld2_v16i8(<32 x i8> *%src, <16 x i8> *%dst) {
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; CHECK-LABEL: vld2_v16i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vld20.8 {q0, q1}, [r0]
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; CHECK-NEXT: vld21.8 {q0, q1}, [r0]!
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; CHECK-NEXT: vadd.i8 q0, q0, q1
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; CHECK-NEXT: vstrw.32 q0, [r1]
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; CHECK-NEXT: bx lr
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entry:
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%l1 = load <32 x i8>, <32 x i8>* %src, align 4
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%s1 = shufflevector <32 x i8> %l1, <32 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
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%s2 = shufflevector <32 x i8> %l1, <32 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
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%a = add <16 x i8> %s1, %s2
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store <16 x i8> %a, <16 x i8> *%dst
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%ret = getelementptr inbounds <32 x i8>, <32 x i8>* %src, i32 1
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ret <32 x i8> *%ret
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}
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; i64
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define <4 x i64> *@vld2_v2i64(<4 x i64> *%src, <2 x i64> *%dst) {
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; CHECK-LABEL: vld2_v2i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .save {r4, r5, r6, lr}
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; CHECK-NEXT: push {r4, r5, r6, lr}
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; CHECK-NEXT: vldrw.u32 q2, [r0, #16]
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; CHECK-NEXT: vldrw.u32 q0, [r0], #32
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; CHECK-NEXT: vmov.f64 d2, d1
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; CHECK-NEXT: vmov.f32 s5, s3
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; CHECK-NEXT: vmov.f32 s6, s10
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; CHECK-NEXT: vmov.f32 s2, s8
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; CHECK-NEXT: vmov.f32 s7, s11
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; CHECK-NEXT: vmov.f32 s3, s9
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; CHECK-NEXT: vmov r2, s6
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; CHECK-NEXT: vmov r3, s2
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; CHECK-NEXT: vmov r4, s4
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; CHECK-NEXT: vmov r5, s0
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; CHECK-NEXT: vmov r12, s7
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; CHECK-NEXT: vmov lr, s3
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; CHECK-NEXT: adds r6, r3, r2
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; CHECK-NEXT: vmov r3, s5
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; CHECK-NEXT: vmov r2, s1
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; CHECK-NEXT: adc.w r12, r12, lr
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; CHECK-NEXT: adds r5, r5, r4
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; CHECK-NEXT: vmov q0[2], q0[0], r5, r6
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; CHECK-NEXT: adcs r2, r3
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; CHECK-NEXT: vmov q0[3], q0[1], r2, r12
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; CHECK-NEXT: vstrw.32 q0, [r1]
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; CHECK-NEXT: pop {r4, r5, r6, pc}
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entry:
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%l1 = load <4 x i64>, <4 x i64>* %src, align 4
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%s1 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 0, i32 2>
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%s2 = shufflevector <4 x i64> %l1, <4 x i64> undef, <2 x i32> <i32 1, i32 3>
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%a = add <2 x i64> %s1, %s2
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store <2 x i64> %a, <2 x i64> *%dst
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%ret = getelementptr inbounds <4 x i64>, <4 x i64>* %src, i32 1
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ret <4 x i64> *%ret
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}
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; f32
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define <8 x float> *@vld2_v4f32(<8 x float> *%src, <4 x float> *%dst) {
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; CHECK-LABEL: vld2_v4f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vld20.32 {q0, q1}, [r0]
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; CHECK-NEXT: vld21.32 {q0, q1}, [r0]!
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; CHECK-NEXT: vadd.f32 q0, q0, q1
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; CHECK-NEXT: vstrw.32 q0, [r1]
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; CHECK-NEXT: bx lr
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entry:
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%l1 = load <8 x float>, <8 x float>* %src, align 4
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%s1 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%s2 = shufflevector <8 x float> %l1, <8 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%a = fadd <4 x float> %s1, %s2
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store <4 x float> %a, <4 x float> *%dst
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%ret = getelementptr inbounds <8 x float>, <8 x float>* %src, i32 1
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ret <8 x float> *%ret
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}
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; f16
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define <16 x half> *@vld2_v8f16(<16 x half> *%src, <8 x half> *%dst) {
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; CHECK-LABEL: vld2_v8f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vld20.16 {q0, q1}, [r0]
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; CHECK-NEXT: vld21.16 {q0, q1}, [r0]!
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; CHECK-NEXT: vadd.f16 q0, q0, q1
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; CHECK-NEXT: vstrw.32 q0, [r1]
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; CHECK-NEXT: bx lr
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entry:
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%l1 = load <16 x half>, <16 x half>* %src, align 4
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%s1 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
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%s2 = shufflevector <16 x half> %l1, <16 x half> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
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%a = fadd <8 x half> %s1, %s2
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store <8 x half> %a, <8 x half> *%dst
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%ret = getelementptr inbounds <16 x half>, <16 x half>* %src, i32 1
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ret <16 x half> *%ret
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}
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; f64
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define <4 x double> *@vld2_v2f64(<4 x double> *%src, <2 x double> *%dst) {
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; CHECK-LABEL: vld2_v2f64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q0, [r0, #16]
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; CHECK-NEXT: vldrw.u32 q1, [r0], #32
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; CHECK-NEXT: vadd.f64 d1, d0, d1
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; CHECK-NEXT: vadd.f64 d0, d2, d3
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; CHECK-NEXT: vstrw.32 q0, [r1]
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; CHECK-NEXT: bx lr
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entry:
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%l1 = load <4 x double>, <4 x double>* %src, align 4
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%s1 = shufflevector <4 x double> %l1, <4 x double> undef, <2 x i32> <i32 0, i32 2>
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%s2 = shufflevector <4 x double> %l1, <4 x double> undef, <2 x i32> <i32 1, i32 3>
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%a = fadd <2 x double> %s1, %s2
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store <2 x double> %a, <2 x double> *%dst
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%ret = getelementptr inbounds <4 x double>, <4 x double>* %src, i32 1
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ret <4 x double> *%ret
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}
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