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8980610845
For a long time, the InstCombine pass handled target specific intrinsics. Having target specific code in general passes was noted as an area for improvement for a long time. D81728 moves most target specific code out of the InstCombine pass. Applying the target specific combinations in an extra pass would probably result in inferior optimizations compared to the current fixed-point iteration, therefore the InstCombine pass resorts to newly introduced functions in the TargetTransformInfo when it encounters unknown intrinsics. The patch should not have any effect on generated code (under the assumption that code never uses intrinsics from a foreign target). This introduces three new functions: TargetTransformInfo::instCombineIntrinsic TargetTransformInfo::simplifyDemandedUseBitsIntrinsic TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic A few target specific parts are left in the InstCombine folder, where it makes sense to share code. The largest left-over part in InstCombineCalls.cpp is the code shared between arm and aarch64. This allows to move about 3000 lines out from InstCombine to the targets. Differential Revision: https://reviews.llvm.org/D81728
45 lines
1.8 KiB
LLVM
45 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: opt -instcombine -mtriple=thumbv8.1m.main-none-eabi %s | llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve --verify-machineinstrs -o - | FileCheck %s
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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define arm_aapcs_vfpcc <8 x i16> @test_vpt_block(<8 x i16> %v_inactive, <8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
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; CHECK-LABEL: test_vpt_block:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.i16 eq, q1, q2
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; CHECK-NEXT: vaddt.i16 q0, q3, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = icmp eq <8 x i16> %v1, %v2
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%1 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %0)
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%2 = trunc i32 %1 to i16
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%3 = zext i16 %2 to i32
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%4 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %3)
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%5 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %v3, <8 x i16> %v2, <8 x i1> %4, <8 x i16> %v_inactive)
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ret <8 x i16> %5
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}
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define arm_aapcs_vfpcc <8 x i16> @test_vpnot(<8 x i16> %v, <8 x i16> %w, <8 x i16> %x, i32 %n) {
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; CHECK-LABEL: test_vpnot:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vctp.16 r0
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; CHECK-NEXT: vpnot
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vaddt.i16 q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <8 x i1> @llvm.arm.mve.vctp16(i32 %n)
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%1 = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> %0)
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%2 = trunc i32 %1 to i16
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%3 = xor i16 %2, -1
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%4 = zext i16 %3 to i32
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%5 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %4)
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%6 = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %w, <8 x i16> %x, <8 x i1> %5, <8 x i16> %v)
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ret <8 x i16> %6
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}
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declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>)
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declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
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declare <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>)
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declare <8 x i1> @llvm.arm.mve.vctp16(i32)
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