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d2bd14842f
The "dead" markings allow existing target-independent optimizations, like MachineSink, to trigger more frequently. The CPSR defs would have eventually been marked dead by LiveVariables, so this only affects optimizations before regalloc. The ARMBaseInstrInfo.cpp change is fixing a bug which is only visible with this change: the transform adds a use to an otherwise dead def of CPSR. This is covered by existing regression tests. thumb2-tbh.ll breaks for Thumb1 due to MachineLICM changing the generated code; I'll fix it in D53452. Differential Revision: https://reviews.llvm.org/D53453 llvm-svn: 345420
104 lines
3.4 KiB
LLVM
104 lines
3.4 KiB
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic | FileCheck %s --check-prefix=CHECK --check-prefix=T2
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; RUN: llc < %s -mtriple=thumbv6m-apple-darwin -relocation-model=pic | FileCheck %s --check-prefix=T1DISABLED
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; FIXME: llc < %s -mtriple=thumbv6m-apple-darwin -relocation-model=pic | FileCheck %s --check-prefix=CHECK --check-prefix=T1
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; FIXME: llc < %s -mtriple=thumbv6m-apple-darwin -relocation-model=static | FileCheck %s --check-prefix=CHECK --check-prefix=T1
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; FIXME: Thumb1 tests temporarily disabled; MachineLICM is now hoisting the
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; subs, so the jump table can't be formed.
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; T1DISABLED: .data_region jt32
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; Thumb2 target should reorder the bb's in order to use tbb / tbh.
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%struct.R_flstr = type { i32, i32, i8* }
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%struct._T_tstr = type { i32, %struct.R_flstr*, %struct._T_tstr* }
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@_C_nextcmd = external global i32 ; <i32*> [#uses=3]
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@.str31 = external constant [28 x i8], align 1 ; <[28 x i8]*> [#uses=1]
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@_T_gtol = external global %struct._T_tstr* ; <%struct._T_tstr**> [#uses=2]
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declare i32 @strlen(i8* nocapture) nounwind readonly
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declare void @Z_fatal(i8*) noreturn nounwind
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declare noalias i8* @calloc(i32, i32) nounwind
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; Jump tables are not anchored next to the TBB/TBH any more. Make sure the
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; correct address is still calculated (i.e. via a PC-relative symbol *at* the
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; TBB/TBH).
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define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
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; CHECK-LABEL: main:
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; CHECK-NOT: adr {{r[0-9]+}}, LJTI
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; T1: lsls r[[x:[0-9]+]], {{r[0-9]+}}, #1
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; CHECK: [[PCREL_ANCHOR:LCPI[0-9]+_[0-9]+]]:
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; T2-NEXT: tbb [pc, {{r[0-9]+}}]
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; T1-NEXT: add pc, r[[x]]
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; CHECK: LJTI0_0:
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; CHECK-NEXT: .data_region jt8
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; CHECK-NEXT: .byte (LBB{{[0-9]+_[0-9]+}}-([[PCREL_ANCHOR]]+4))/2
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entry:
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br label %bb42.i
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bb1.i2: ; preds = %bb42.i
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br label %bb40.i
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bb5.i: ; preds = %bb42.i
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%0 = or i32 %argc, 32 ; <i32> [#uses=1]
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br label %bb40.i
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bb7.i: ; preds = %bb42.i
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call void @_T_addtol(%struct._T_tstr** @_T_gtol, i32 0, i8* null) nounwind
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unreachable
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bb15.i: ; preds = %bb42.i
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call void @_T_addtol(%struct._T_tstr** @_T_gtol, i32 2, i8* null) nounwind
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unreachable
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bb23.i: ; preds = %bb42.i
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%1 = call i32 @strlen(i8* null) nounwind readonly ; <i32> [#uses=0]
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unreachable
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bb33.i: ; preds = %bb42.i
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store i32 0, i32* @_C_nextcmd, align 4
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%2 = call noalias i8* @calloc(i32 21, i32 1) nounwind ; <i8*> [#uses=0]
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unreachable
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bb34.i: ; preds = %bb42.i
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%3 = load i32, i32* @_C_nextcmd, align 4 ; <i32> [#uses=1]
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%4 = add i32 %3, 1 ; <i32> [#uses=1]
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store i32 %4, i32* @_C_nextcmd, align 4
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%5 = call noalias i8* @calloc(i32 22, i32 1) nounwind ; <i8*> [#uses=0]
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unreachable
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bb35.i: ; preds = %bb42.i
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%6 = call noalias i8* @calloc(i32 20, i32 1) nounwind ; <i8*> [#uses=0]
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unreachable
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bb37.i: ; preds = %bb42.i
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%7 = call noalias i8* @calloc(i32 14, i32 1) nounwind ; <i8*> [#uses=0]
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unreachable
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bb39.i: ; preds = %bb42.i
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call void @Z_fatal(i8* getelementptr ([28 x i8], [28 x i8]* @.str31, i32 0, i32 0)) nounwind
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unreachable
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bb40.i: ; preds = %bb42.i, %bb5.i, %bb1.i2
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br label %bb42.i
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bb42.i: ; preds = %bb40.i, %entry
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switch i32 %argc, label %bb39.i [
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i32 67, label %bb33.i
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i32 70, label %bb35.i
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i32 77, label %bb37.i
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i32 83, label %bb34.i
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i32 97, label %bb7.i
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i32 100, label %bb5.i
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i32 101, label %bb40.i
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i32 102, label %bb23.i
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i32 105, label %bb15.i
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i32 116, label %bb1.i2
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]
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}
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declare void @_T_addtol(%struct._T_tstr** nocapture, i32, i8*) nounwind
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