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c2db7efb6c
This patch complements D16810 "[mips] Make isel select the correct DEXT variant up front.". Now ISel picks the right variant of DINS, so now there is no need to replace DINS with the appropriate variant during MipsMCCodeEmitter::encodeInstruction(). This patch also enables target specific instruction verification for ins, dins, dinsm, dinsu, ext, dext, dextm, dextu. These instructions have constraints that are checked when generating MipsISD::Ins and MipsISD::Ext nodes, but these constraints are not checked during instruction selection. Adding machine verification should catch outstanding cases. Finally, correct a bug that instruction verification uncovered, where the position operand of a DINSU generated during lowering was being silently and accidently corrected to the correct value. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D34809 llvm-svn: 313254
50 lines
1.2 KiB
YAML
50 lines
1.2 KiB
YAML
# RUN: not llc -march=mips64 -mcpu=mips64r2 -start-after=expand-isel-pseudos -stop-after=expand-isel-pseudos \
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# RUN: -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
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# CHECK: Position + Size is out of range!
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# Check that the machine verifier checks the pos + size is in range 0..32
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---
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name: dins
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alignment: 3
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr64, preferred-register: '' }
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- { id: 1, class: gpr64, preferred-register: '' }
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liveins:
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- { reg: '%a0_64', virtual-reg: '%0' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 1
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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savePoint: ''
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restorePoint: ''
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fixedStack:
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stack:
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constants:
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body: |
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bb.0.entry:
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liveins: %a0_64
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%0 = COPY %a0_64
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%1 = DINS %0, 17, 17
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%v0_64 = COPY %1
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RetRA implicit %v0_64
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...
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