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llvm-mirror/test/MC/Disassembler/arm-tests.txt
Jim Grosbach 1699d40f80 Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

llvm-svn: 116432
2010-10-13 21:00:04 +00:00

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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s
# CHECK: b #0
0xfe 0xff 0xff 0xea
# CHECK: bfc r8, #0, #16
0x1f 0x80 0xcf 0xe7
# CHECK: bfi r8, r0, #16, #1
0x10 0x88 0xd0 0xe7
# CHECK: cmn r0, #1
0x01 0x00 0x70 0xe3
# CHECK: dmb
0x5f 0xf0 0x7f 0xf5
# CHECK: dmb nshst
0x56 0xf0 0x7f 0xf5
# CHECK: dsb
0x4f 0xf0 0x7f 0xf5
# CHECK: dsb st
0x4e 0xf0 0x7f 0xf5
# CHECK: isb
0x6f 0xf0 0x7f 0xf5
# CHECK: ldclvc p5, cr15, [r8], #-0
0x00 0xf5 0x78 0x7c
# CHECK: ldr r0, [r2], #15
0x0f 0x00 0x92 0xe4
# CHECK: ldrh r0, [r2], #0
0xb0 0x00 0xd2 0xe0
# CHECK: ldrht r0, [r2], #15
0xbf 0x00 0xf2 0xe0
# CHECK: ldrsbtvs lr, [r2], -r9
0xd9 0xe9 0x32 0x60
# CHECK: lsls r0, r2, #31
0x82 0x0f 0xb0 0xe1
# CHECK: mcr2 p0, #0, r2, cr1, cr0, #7
0xf0 0x20 0x01 0xfe
# CHECK: movt r8, #65535
0xff 0x8f 0x4f 0xe3
# CHECK: mvnpls r7, #245, 2
0xf5 0x71 0xf0 0x53
# CHECK-NOT: orr r7, r8, r7, rrx #0
# CHECK: orr r7, r8, r7, rrx
0x67 0x70 0x88 0xe1
# CHECK: pkhbt r8, r9, r10, lsl #4
0x1a 0x82 0x89 0xe6
# CHECK-NOT: pkhbtls pc, r11, r11, lsl #0
# CHECK: pkhbtls pc, r11, r11
0x1b 0xf0 0x8b 0x96
# CHECK: pop {r0, r2, r4, r6, r8, r10}
0x55 0x05 0xbd 0xe8
# CHECK: push {r0, r2, r4, r6, r8, r10}
0x55 0x05 0x2d 0xe9
# CHECK: qsax r8, r9, r10
0x5a 0x8f 0x29 0xe6
# CHECK: rfedb r0!
0x00 0x0a 0x30 0xf9
# CHECK-NOT: rsbeq r0, r2, r0, lsl #0
# CHECK: rsbeq r0, r2, r0
0x00 0x00 0x62 0x00
# CHECK-NOT: rsceqs r0, r0, r1, lsl #0
# CHECK: rsceqs r0, r0, r1
0x01 0x00 0xf0 0x00
# CHECK: sbcs r0, pc, #1
0x01 0x00 0xdf 0xe2
# CHECK: sbfx r0, r1, #0, #8
0x51 0x00 0xa7 0xe7
# CHECK: ssat r8, #1, r10, lsl #8
0x1a 0x84 0xa0 0xe6
# CHECK-NOT: ssatmi r0, #17, r12, lsl #0
# CHECK: ssatmi r0, #17, r12
0x1c 0x00 0xb0 0x46
# CHECK: stmdb r10!, {r4, r5, r6, r7, lr}
0xf0 0x40 0x2a 0xe9
# CHECK: teq r0, #31
0x1f 0x00 0x30 0xe3
# CHECK: ubfx r0, r0, #16, #1
0x50 0x08 0xe0 0xe7
# CHECK: usat r8, #0, r10, asr #32
0x5a 0x80 0xe0 0xe6
# CHECK: setend be
0x00 0x02 0x01 0xf1
# CHECK: setend le
0x00 0x00 0x01 0xf1