Daniel Sanders 1dc46d2fa0 [globalisel][tablegen] Add support for RegisterOperand. ... Summary: It functions just like RegisterClass except that the class is obtained from a field. Depends on D31761. Reviewers: ab, qcolombet, t.p.northover, rovka, kristof.beyls, aditya_nandakumar Reviewed By: ab Subscribers: dberris, llvm-commits, igorb Differential Revision: https://reviews.llvm.org/D32229 llvm-svn: 301080		2017-04-22 15:53:21 +00:00
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2003-08-03-PassCode.td
2006-09-18-LargeInt.td
2010-03-24-PrematureDefaults.td
AnonDefinitionOnDemand.td
AsmPredicateCondsEmission.td
AsmVariant.td	[TableGen] AsmMatcher: Add AsmVariantName to Instruction class.	2016-09-08 15:50:52 +00:00
BitOffsetDecoder.td
BitsInit.td
BitsInitOverflow.td
cast-list-initializer.td
cast.td
ClassInstanceValue.td
CStyleComment.td
Dag.td
defmclass.td
DefmInherit.td
DefmInsideMultiClass.td
DuplicateFieldValues.td	[tablegen] Delete duplicates from a vector without skipping elements	2016-12-01 19:38:50 +00:00
eq.td
eqbit.td
FieldAccess.td
foreach.td
ForeachList.td
ForeachLoop.td
ForwardRef.td
GeneralList.td
GlobalISelEmitter.td	[globalisel][tablegen] Add support for RegisterOperand.	2017-04-22 15:53:21 +00:00
if-empty-list-arg.td
if.td
ifbit.td
Include.inc
Include.td
IntBitInit.td
intrinsic-long-name.td	[MVT][SVE] Scalable vector MVTs (2/3)	2017-04-20 13:36:58 +00:00
intrinsic-varargs.td	[MVT][SVE] Scalable vector MVTs (2/3)	2017-04-20 13:36:58 +00:00
LazyChange.td
LetInsideMultiClasses.td
lisp.td
list-element-bitref.td
ListArgs.td
ListArgsSimple.td
listconcat.td
ListConversion.td
ListManip.td
ListOfList.td
ListSlices.td
lit.local.cfg
LoLoL.td
math.td	TableGen: Add operator !or	2016-11-15 06:49:28 +00:00
MultiClass.td
MultiClassDefName.td
MultiClassInherit.td
MultiPat.td
nested-comment.td
NestedForeach.td
Paste.td
pr8330.td
RegisterBankEmitter.td	TableGen: Fix infinite recursion in RegisterBankEmitter	2017-01-30 15:07:01 +00:00
SetTheory.td
SiblingForeach.td
Slice.td
strconcat.td
String.td
subst2.td
subst.td
SuperSubclassSameName.td
TargetInstrInfo.td
TargetInstrSpec.td
TemplateArgRename.td
Tree.td
TreeNames.td
trydecode-emission2.td	tests: accept different TargetOpcode values.	2016-07-07 17:51:42 +00:00
trydecode-emission3.td	tests: accept different TargetOpcode values.	2016-07-07 17:51:42 +00:00
trydecode-emission.td	tests: accept different TargetOpcode values.	2016-07-07 17:51:42 +00:00
TwoLevelName.td	Add test cases that will show the bug that was fixed in r256725.	2016-01-13 07:53:11 +00:00
UnsetBitInit.td
UnterminatedComment.td
usevalname.td
ValidIdentifiers.td