Geoff Berry 6d2bb54f01 [AArch64] Favor extended reg patterns for sub ... Summary: Favor the extended reg patterns over the shifted reg patterns that match only the operand shift and not the full sign/zero extend and shift. Reviewers: jmolloy, t.p.northover Subscribers: mcrosier, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D11569 llvm-svn: 243753		2015-07-31 15:55:54 +00:00
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AArch64	[AArch64] Favor extended reg patterns for sub	2015-07-31 15:55:54 +00:00
AMDGPU	AMDGPU: Fix v16i32 to v16i8 truncstore	2015-07-31 04:12:04 +00:00
ARM	[ARM] Lower modulo operation to generate __aeabi_divmod on Android	2015-07-31 00:45:12 +00:00
BPF
CPP
Generic	Move unit tests to target specific directories.	2015-07-28 17:32:49 +00:00
Hexagon	[Hexagon] Generate MUX from conditional transfers when dot-new not possible	2015-07-20 21:23:25 +00:00
Inputs
Mips	[mips][FastISel] Remove hidden mips-fast-isel option.	2015-07-30 12:39:33 +00:00
MIR	MIR Parser: Report an error when a constant pool item is redefined.	2015-07-30 22:00:17 +00:00
MSP430
NVPTX	Roll forward r242871	2015-07-29 18:59:09 +00:00
PowerPC	[PPC] Fix PR24216: Don't generate splat for misaligned shuffle mask	2015-07-29 14:31:57 +00:00
SPARC	[SPARC] Cleanup handling of the Y/ASR registers.	2015-07-08 16:25:12 +00:00
SystemZ
Thumb	[ARM] Define subtarget feature strict-align.	2015-07-28 22:44:28 +00:00
Thumb2	ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2	2015-07-21 00:18:59 +00:00
WebAssembly	WebAssembly: add a generic CPU	2015-07-27 23:25:54 +00:00
WinEH	[WinEH] Strip the \01 character from the __CxxFrameHandler3 thunk name	2015-07-13 17:55:14 +00:00
X86	fix memcpy/memset/memmove lowering when optimizing for size	2015-07-30 21:41:50 +00:00
XCore