1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-19 02:52:53 +02:00
llvm-mirror/test/CodeGen
Craig Topper 9d88bde411 [X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.
INC/DEC is really a special case of a more generic issue. We should also turn leas into add reg/reg or add reg/imm regardless of the slow lea flags.

This also supports LEA64_32 which has 64 bit input registers and 32 bit output registers. So we need to convert the 64 bit inputs to their 32 bit equivalents to check if they are equal to base reg.

One thing to note, the original code preserved the kill flags by adding operands to the new instruction instead of using addReg. But I think tied operands aren't supposed to have the kill flag set. I dropped the kill flags, but I could probably try to preserve it in the add reg/reg case if we think its important. Not sure which operand its supposed to go on for the LEA64_32r instruction due to the super reg implicit uses. Though I'm also not sure those are needed since they were probably just created by an INSERT_SUBREG from a 32-bit input.

Differential Revision: https://reviews.llvm.org/D61472

llvm-svn: 361691
2019-05-25 06:17:47 +00:00
..
AArch64 [GlobalISel][AArch64] Make FP constraint checks consider possible use/def banks 2019-05-24 23:08:45 +00:00
AMDGPU Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for cross block values according to the divergence." 2019-05-25 01:52:38 +00:00
ARC
ARM [ARM][CGP] Clear SafeWrap before each search 2019-05-23 07:46:39 +00:00
AVR Add TargetLoweringInfo hook for explicitly setting the ABI calling convention endianess 2019-05-21 06:38:02 +00:00
BPF
Generic [IR] allow fast-math-flags on select of FP values 2019-05-22 15:50:46 +00:00
Hexagon
Inputs
Lanai
Mips [mips] Always check that shift and add optimization is efficient. 2019-05-24 08:39:40 +00:00
MIR
MSP430
NVPTX
PowerPC Implement call lowering without parameters on AIX 2019-05-24 20:54:35 +00:00
RISCV [RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV 2019-05-23 12:43:13 +00:00
SPARC [TargetLowering] Extend bool args to inline-asm according to getBooleanType 2019-05-22 16:16:15 +00:00
SystemZ [TargetLowering] Extend bool args to inline-asm according to getBooleanType 2019-05-22 16:16:15 +00:00
Thumb [TargetLowering] Extend bool args to inline-asm according to getBooleanType 2019-05-22 16:16:15 +00:00
Thumb2 [TargetLowering] Extend bool args to inline-asm according to getBooleanType 2019-05-22 16:16:15 +00:00
WebAssembly [WebAssembly] Expand more SIMD float ops 2019-05-24 00:15:04 +00:00
WinCFGuard
WinEH
X86 [X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly. 2019-05-25 06:17:47 +00:00
XCore