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d875c88104
The usual way to get a 32-bit relocation is to use a constant extender which doubles the size of the instruction, 4 bytes to 8 bytes. Another way is to put a .word32 and mix code and data within a function. The disadvantage is it's not a valid instruction encoding and jumping over it causes prefetch stalls inside the hardware. This relocation packs a 23-bit value in to an "r0 = add(rX, #a)" instruction by overwriting the source register bits. Since r0 is the return value register, if this instruction is placed after a function call which return void, r0 will be filled with an undefined value, the prefetch won't be confused, and the callee can access the constant value by way of the link register. llvm-svn: 261006
298 lines
11 KiB
C++
298 lines
11 KiB
C++
//===- HexagonMCInstrInfo.cpp - Utility functions on Hexagon MCInsts ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Utility functions for Hexagon specific MCInst queries
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
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#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
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#include "HexagonMCExpr.h"
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#include "llvm/MC/MCInst.h"
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namespace llvm {
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class HexagonMCChecker;
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class MCContext;
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class MCInstrDesc;
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class MCInstrInfo;
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class MCInst;
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class MCOperand;
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class MCSubtargetInfo;
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namespace HexagonII {
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enum class MemAccessSize;
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}
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class DuplexCandidate {
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public:
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unsigned packetIndexI, packetIndexJ, iClass;
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DuplexCandidate(unsigned i, unsigned j, unsigned iClass)
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: packetIndexI(i), packetIndexJ(j), iClass(iClass) {}
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};
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namespace HexagonMCInstrInfo {
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size_t const innerLoopOffset = 0;
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int64_t const innerLoopMask = 1 << innerLoopOffset;
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size_t const outerLoopOffset = 1;
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int64_t const outerLoopMask = 1 << outerLoopOffset;
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// do not reorder memory load/stores by default load/stores are re-ordered
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// and by default loads can be re-ordered
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size_t const memReorderDisabledOffset = 2;
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int64_t const memReorderDisabledMask = 1 << memReorderDisabledOffset;
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// allow re-ordering of memory stores by default stores cannot be re-ordered
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size_t const memStoreReorderEnabledOffset = 3;
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int64_t const memStoreReorderEnabledMask = 1 << memStoreReorderEnabledOffset;
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size_t const bundleInstructionsOffset = 1;
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void addConstant(MCInst &MI, uint64_t Value, MCContext &Context);
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void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
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MCInst const &MCI);
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// Returns a iterator range of instructions in this bundle
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iterator_range<MCInst::const_iterator> bundleInstructions(MCInst const &MCI);
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// Returns the number of instructions in the bundle
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size_t bundleSize(MCInst const &MCI);
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// Put the packet in to canonical form, compound, duplex, pad, and shuffle
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bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
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MCContext &Context, MCInst &MCB,
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HexagonMCChecker *Checker);
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// Clamp off upper 26 bits of extendable operand for emission
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void clampExtended(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI);
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MCInst createBundle();
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// Return the extender for instruction at Index or nullptr if none
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MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);
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void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
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MCInst const &MCI, bool MustExtend);
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// Create a duplex instruction given the two subinsts
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MCInst *deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0,
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MCInst const &inst1);
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MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,
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MCOperand const &MO);
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// Convert this instruction in to a duplex subinst
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MCInst deriveSubInst(MCInst const &Inst);
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// Return the extender for instruction at Index or nullptr if none
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MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);
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// Return memory access size
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HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII,
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MCInst const &MCI);
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// Return number of bits in the constant extended operand.
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unsigned getBitCount(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return constant extended operand number.
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unsigned short getCExtOpNum(MCInstrInfo const &MCII, MCInst const &MCI);
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MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return which duplex group this instruction belongs to
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unsigned getDuplexCandidateGroup(MCInst const &MI);
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// Return a list of all possible instruction duplex combinations
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SmallVector<DuplexCandidate, 8> getDuplexPossibilties(MCInstrInfo const &MCII,
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MCInst const &MCB);
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MCExpr const &getExpr(MCExpr const &Expr);
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// Return the index of the extendable operand
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unsigned short getExtendableOp(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return a reference to the extendable operand
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MCOperand const &getExtendableOperand(MCInstrInfo const &MCII,
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MCInst const &MCI);
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// Return the implicit alignment of the extendable operand
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unsigned getExtentAlignment(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return the number of logical bits of the extendable operand
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unsigned getExtentBits(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return the max value that a constant extendable operand can have
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// without being extended.
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int getMaxValue(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return the min value that a constant extendable operand can have
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// without being extended.
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int getMinValue(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return instruction name
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char const *getName(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return the operand index for the new value.
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unsigned short getNewValueOp(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return the operand that consumes or produces a new value.
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MCOperand const &getNewValueOperand(MCInstrInfo const &MCII, MCInst const &MCI);
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unsigned short getNewValueOp2(MCInstrInfo const &MCII, MCInst const &MCI);
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MCOperand const &getNewValueOperand2(MCInstrInfo const &MCII,
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MCInst const &MCI);
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int getSubTarget(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return the Hexagon ISA class for the insn.
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unsigned getType(MCInstrInfo const &MCII, MCInst const &MCI);
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/// Return the slots used by the insn.
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unsigned getUnits(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
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MCInst const &MCI);
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// Does the packet have an extender for the instruction at Index
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bool hasExtenderForIndex(MCInst const &MCB, size_t Index);
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bool hasImmExt(MCInst const &MCI);
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// Return whether the instruction is a legal new-value producer.
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bool hasNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
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bool hasNewValue2(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return the instruction at Index
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MCInst const &instruction(MCInst const &MCB, size_t Index);
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// Returns whether this MCInst is a wellformed bundle
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bool isBundle(MCInst const &MCI);
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// Return whether the insn is an actual insn.
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bool isCanon(MCInstrInfo const &MCII, MCInst const &MCI);
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bool isCompound(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return the duplex iclass given the two duplex classes
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unsigned iClassOfDuplexPair(unsigned Ga, unsigned Gb);
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int64_t minConstant(MCInst const &MCI, size_t Index);
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template <unsigned N, unsigned S>
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bool inRange(MCInst const &MCI, size_t Index) {
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return isShiftedUInt<N, S>(minConstant(MCI, Index));
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}
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template <unsigned N, unsigned S>
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bool inSRange(MCInst const &MCI, size_t Index) {
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return isShiftedInt<N, S>(minConstant(MCI, Index));
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}
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template <unsigned N> bool inRange(MCInst const &MCI, size_t Index) {
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return isUInt<N>(minConstant(MCI, Index));
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}
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// Return whether the instruction needs to be constant extended.
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bool isConstExtended(MCInstrInfo const &MCII, MCInst const &MCI);
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// Is this double register suitable for use in a duplex subinst
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bool isDblRegForSubInst(unsigned Reg);
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// Is this a duplex instruction
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bool isDuplex(MCInstrInfo const &MCII, MCInst const &MCI);
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// Can these instructions be duplexed
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bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
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// Can these duplex classes be combine in to a duplex instruction
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bool isDuplexPairMatch(unsigned Ga, unsigned Gb);
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// Return true if the insn may be extended based on the operand value.
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bool isExtendable(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return whether the instruction must be always extended.
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bool isExtended(MCInstrInfo const &MCII, MCInst const &MCI);
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/// Return whether it is a floating-point insn.
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bool isFloat(MCInstrInfo const &MCII, MCInst const &MCI);
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// Returns whether this instruction is an immediate extender
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bool isImmext(MCInst const &MCI);
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// Returns whether this bundle is an endloop0
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bool isInnerLoop(MCInst const &MCI);
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// Is this an integer register
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bool isIntReg(unsigned Reg);
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// Is this register suitable for use in a duplex subinst
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bool isIntRegForSubInst(unsigned Reg);
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bool isMemReorderDisabled(MCInst const &MCI);
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bool isMemStoreReorderEnabled(MCInst const &MCI);
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// Return whether the insn is a new-value consumer.
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bool isNewValue(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return true if the operand can be constant extended.
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bool isOperandExtended(MCInstrInfo const &MCII, MCInst const &MCI,
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unsigned short OperandNum);
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// Can these two instructions be duplexed
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bool isOrderedDuplexPair(MCInstrInfo const &MCII, MCInst const &MIa,
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bool ExtendedA, MCInst const &MIb, bool ExtendedB,
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bool bisReversable);
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// Returns whether this bundle is an endloop1
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bool isOuterLoop(MCInst const &MCI);
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// Return whether this instruction is predicated
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bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
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bool isPredicateLate(MCInstrInfo const &MCII, MCInst const &MCI);
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bool isPredicatedNew(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return whether the predicate sense is true
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bool isPredicatedTrue(MCInstrInfo const &MCII, MCInst const &MCI);
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// Is this a predicate register
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bool isPredReg(unsigned Reg);
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// Return whether the insn is a prefix.
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bool isPrefix(MCInstrInfo const &MCII, MCInst const &MCI);
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// Return whether the insn is solo, i.e., cannot be in a packet.
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bool isSolo(MCInstrInfo const &MCII, MCInst const &MCI);
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/// Return whether the insn can be packaged only with A and X-type insns.
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bool isSoloAX(MCInstrInfo const &MCII, MCInst const &MCI);
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/// Return whether the insn can be packaged only with an A-type insn in slot #1.
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bool isSoloAin1(MCInstrInfo const &MCII, MCInst const &MCI);
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bool isVector(MCInstrInfo const &MCII, MCInst const &MCI);
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bool mustExtend(MCExpr const &Expr);
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bool mustNotExtend(MCExpr const &Expr);
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// Pad the bundle with nops to satisfy endloop requirements
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void padEndloop(MCContext &Context, MCInst &MCI);
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bool prefersSlot3(MCInstrInfo const &MCII, MCInst const &MCI);
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// Replace the instructions inside MCB, represented by Candidate
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void replaceDuplex(MCContext &Context, MCInst &MCB, DuplexCandidate Candidate);
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bool s23_2_reloc(MCExpr const &Expr);
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// Marks a bundle as endloop0
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void setInnerLoop(MCInst &MCI);
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void setMemReorderDisabled(MCInst &MCI);
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void setMemStoreReorderEnabled(MCInst &MCI);
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void setMustExtend(MCExpr &Expr, bool Val = true);
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void setMustNotExtend(MCExpr const &Expr, bool Val = true);
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void setS23_2_reloc(MCExpr const &Expr, bool Val = true);
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// Marks a bundle as endloop1
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void setOuterLoop(MCInst &MCI);
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// Would duplexing this instruction create a requirement to extend
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bool subInstWouldBeExtended(MCInst const &potentialDuplex);
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// Attempt to find and replace compound pairs
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void tryCompound(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI);
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}
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}
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#endif // LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINSTRINFO_H
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