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ed5decd2c8
Summary: While clustering mem ops, AMDGPU target needs to consider number of clustered bytes to decide on max number of mem ops that can be clustered. This patch adds support to pass number of clustered bytes to target mem ops clustering logic. Reviewers: foad, rampitec, arsenm, vpykhtin, javedabsar Reviewed By: foad Subscribers: MatzeB, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, javed.absar, kerbowa, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D80545
440 lines
20 KiB
C++
440 lines
20 KiB
C++
//===- AArch64InstrInfo.h - AArch64 Instruction Information -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the AArch64 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64INSTRINFO_H
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#include "AArch64.h"
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#include "AArch64RegisterInfo.h"
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#include "AArch64StackOffset.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/CodeGen/MachineCombinerPattern.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/Support/TypeSize.h"
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#define GET_INSTRINFO_HEADER
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#include "AArch64GenInstrInfo.inc"
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namespace llvm {
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class AArch64Subtarget;
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class AArch64TargetMachine;
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static const MachineMemOperand::Flags MOSuppressPair =
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MachineMemOperand::MOTargetFlag1;
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static const MachineMemOperand::Flags MOStridedAccess =
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MachineMemOperand::MOTargetFlag2;
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#define FALKOR_STRIDED_ACCESS_MD "falkor.strided.access"
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class AArch64InstrInfo final : public AArch64GenInstrInfo {
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const AArch64RegisterInfo RI;
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const AArch64Subtarget &Subtarget;
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public:
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explicit AArch64InstrInfo(const AArch64Subtarget &STI);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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const AArch64RegisterInfo &getRegisterInfo() const { return RI; }
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unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
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bool isAsCheapAsAMove(const MachineInstr &MI) const override;
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bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg,
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Register &DstReg, unsigned &SubIdx) const override;
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bool
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areMemAccessesTriviallyDisjoint(const MachineInstr &MIa,
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const MachineInstr &MIb) const override;
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unsigned isLoadFromStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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unsigned isStoreToStackSlot(const MachineInstr &MI,
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int &FrameIndex) const override;
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/// Does this instruction set its full destination register to zero?
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static bool isGPRZero(const MachineInstr &MI);
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/// Does this instruction rename a GPR without modifying bits?
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static bool isGPRCopy(const MachineInstr &MI);
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/// Does this instruction rename an FPR without modifying bits?
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static bool isFPRCopy(const MachineInstr &MI);
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/// Return true if pairing the given load or store is hinted to be
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/// unprofitable.
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static bool isLdStPairSuppressed(const MachineInstr &MI);
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/// Return true if the given load or store is a strided memory access.
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static bool isStridedAccess(const MachineInstr &MI);
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/// Return true if this is an unscaled load/store.
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static bool isUnscaledLdSt(unsigned Opc);
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static bool isUnscaledLdSt(MachineInstr &MI) {
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return isUnscaledLdSt(MI.getOpcode());
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}
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/// Returns the unscaled load/store for the scaled load/store opcode,
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/// if there is a corresponding unscaled variant available.
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static Optional<unsigned> getUnscaledLdSt(unsigned Opc);
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/// Scaling factor for (scaled or unscaled) load or store.
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static int getMemScale(unsigned Opc);
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static int getMemScale(const MachineInstr &MI) {
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return getMemScale(MI.getOpcode());
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}
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/// Returns the index for the immediate for a given instruction.
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static unsigned getLoadStoreImmIdx(unsigned Opc);
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/// Return true if pairing the given load or store may be paired with another.
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static bool isPairableLdStInst(const MachineInstr &MI);
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/// Return the opcode that set flags when possible. The caller is
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/// responsible for ensuring the opc has a flag setting equivalent.
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static unsigned convertToFlagSettingOpc(unsigned Opc, bool &Is64Bit);
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/// Return true if this is a load/store that can be potentially paired/merged.
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bool isCandidateToMergeOrPair(const MachineInstr &MI) const;
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/// Hint that pairing the given load or store is unprofitable.
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static void suppressLdStPair(MachineInstr &MI);
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bool getMemOperandsWithOffsetWidth(
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const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps,
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int64_t &Offset, bool &OffsetIsScalable, unsigned &Width,
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const TargetRegisterInfo *TRI) const override;
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/// If \p OffsetIsScalable is set to 'true', the offset is scaled by `vscale`.
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/// This is true for some SVE instructions like ldr/str that have a
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/// 'reg + imm' addressing mode where the immediate is an index to the
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/// scalable vector located at 'reg + imm * vscale x #bytes'.
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bool getMemOperandWithOffsetWidth(const MachineInstr &MI,
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const MachineOperand *&BaseOp,
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int64_t &Offset, bool &OffsetIsScalable,
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unsigned &Width,
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const TargetRegisterInfo *TRI) const;
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/// Return the immediate offset of the base register in a load/store \p LdSt.
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MachineOperand &getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const;
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/// Returns true if opcode \p Opc is a memory operation. If it is, set
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/// \p Scale, \p Width, \p MinOffset, and \p MaxOffset accordingly.
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///
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/// For unscaled instructions, \p Scale is set to 1.
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static bool getMemOpInfo(unsigned Opcode, TypeSize &Scale, unsigned &Width,
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int64_t &MinOffset, int64_t &MaxOffset);
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bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1,
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ArrayRef<const MachineOperand *> BaseOps2,
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unsigned NumLoads, unsigned NumBytes) const override;
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void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const DebugLoc &DL, MCRegister DestReg,
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MCRegister SrcReg, bool KillSrc, unsigned Opcode,
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llvm::ArrayRef<unsigned> Indices) const;
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void copyGPRRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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DebugLoc DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc, unsigned Opcode, unsigned ZeroReg,
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llvm::ArrayRef<unsigned> Indices) const;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, Register SrcReg,
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bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI, Register DestReg,
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int FrameIndex, const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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// This tells target independent code that it is okay to pass instructions
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// with subreg operands to foldMemoryOperandImpl.
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bool isSubregFoldable() const override { return true; }
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using TargetInstrInfo::foldMemoryOperandImpl;
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MachineInstr *
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foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
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ArrayRef<unsigned> Ops,
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MachineBasicBlock::iterator InsertPt, int FrameIndex,
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LiveIntervals *LIS = nullptr,
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VirtRegMap *VRM = nullptr) const override;
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/// \returns true if a branch from an instruction with opcode \p BranchOpc
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/// bytes is capable of jumping to a position \p BrOffset bytes away.
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bool isBranchOffsetInRange(unsigned BranchOpc,
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int64_t BrOffset) const override;
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MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override;
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bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify = false) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved = nullptr) const override;
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unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded = nullptr) const override;
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bool
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reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond,
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Register, Register, Register, int &, int &,
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int &) const override;
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void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const DebugLoc &DL, Register DstReg,
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ArrayRef<MachineOperand> Cond, Register TrueReg,
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Register FalseReg) const override;
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void getNoop(MCInst &NopInst) const override;
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bool isSchedulingBoundary(const MachineInstr &MI,
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const MachineBasicBlock *MBB,
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const MachineFunction &MF) const override;
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/// analyzeCompare - For a comparison instruction, return the source registers
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/// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
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/// Return true if the comparison instruction can be analyzed.
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bool analyzeCompare(const MachineInstr &MI, Register &SrcReg,
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Register &SrcReg2, int &CmpMask,
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int &CmpValue) const override;
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/// optimizeCompareInstr - Convert the instruction supplying the argument to
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/// the comparison into one that sets the zero bit in the flags register.
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bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
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Register SrcReg2, int CmpMask, int CmpValue,
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const MachineRegisterInfo *MRI) const override;
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bool optimizeCondBranch(MachineInstr &MI) const override;
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/// Return true when a code sequence can improve throughput. It
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/// should be called only for instructions in loops.
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/// \param Pattern - combiner pattern
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bool isThroughputPattern(MachineCombinerPattern Pattern) const override;
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/// Return true when there is potentially a faster code sequence
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/// for an instruction chain ending in ``Root``. All potential patterns are
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/// listed in the ``Patterns`` array.
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bool getMachineCombinerPatterns(
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MachineInstr &Root,
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SmallVectorImpl<MachineCombinerPattern> &Patterns) const override;
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/// Return true when Inst is associative and commutative so that it can be
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/// reassociated.
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bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
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/// When getMachineCombinerPatterns() finds patterns, this function generates
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/// the instructions that could replace the original code sequence
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void genAlternativeCodeSequence(
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MachineInstr &Root, MachineCombinerPattern Pattern,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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SmallVectorImpl<MachineInstr *> &DelInstrs,
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DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
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/// AArch64 supports MachineCombiner.
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bool useMachineCombiner() const override;
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bool expandPostRAPseudo(MachineInstr &MI) const override;
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std::pair<unsigned, unsigned>
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decomposeMachineOperandsTargetFlags(unsigned TF) const override;
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableDirectMachineOperandTargetFlags() const override;
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ArrayRef<std::pair<unsigned, const char *>>
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getSerializableBitmaskMachineOperandTargetFlags() const override;
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ArrayRef<std::pair<MachineMemOperand::Flags, const char *>>
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getSerializableMachineMemOperandTargetFlags() const override;
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bool isFunctionSafeToOutlineFrom(MachineFunction &MF,
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bool OutlineFromLinkOnceODRs) const override;
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outliner::OutlinedFunction getOutliningCandidateInfo(
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std::vector<outliner::Candidate> &RepeatedSequenceLocs) const override;
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outliner::InstrType
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getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const override;
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bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB,
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unsigned &Flags) const override;
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void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF,
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const outliner::OutlinedFunction &OF) const override;
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MachineBasicBlock::iterator
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insertOutlinedCall(Module &M, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &It, MachineFunction &MF,
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const outliner::Candidate &C) const override;
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bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const override;
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/// Returns the vector element size (B, H, S or D) of an SVE opcode.
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uint64_t getElementSizeForOpcode(unsigned Opc) const;
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/// Returns true if the instruction has a shift by immediate that can be
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/// executed in one cycle less.
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static bool isFalkorShiftExtFast(const MachineInstr &MI);
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/// Return true if the instructions is a SEH instruciton used for unwinding
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/// on Windows.
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static bool isSEHInstruction(const MachineInstr &MI);
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Optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
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Register Reg) const override;
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Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI,
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Register Reg) const override;
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#define GET_INSTRINFO_HELPER_DECLS
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#include "AArch64GenInstrInfo.inc"
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protected:
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/// If the specific machine instruction is an instruction that moves/copies
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/// value from one register to another register return destination and source
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/// registers as machine operands.
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Optional<DestSourcePair>
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isCopyInstrImpl(const MachineInstr &MI) const override;
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private:
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unsigned getInstBundleLength(const MachineInstr &MI) const;
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/// Sets the offsets on outlined instructions in \p MBB which use SP
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/// so that they will be valid post-outlining.
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///
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/// \param MBB A \p MachineBasicBlock in an outlined function.
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void fixupPostOutline(MachineBasicBlock &MBB) const;
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void instantiateCondBranch(MachineBasicBlock &MBB, const DebugLoc &DL,
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MachineBasicBlock *TBB,
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ArrayRef<MachineOperand> Cond) const;
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bool substituteCmpToZero(MachineInstr &CmpInstr, unsigned SrcReg,
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const MachineRegisterInfo *MRI) const;
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/// Returns an unused general-purpose register which can be used for
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/// constructing an outlined call if one exists. Returns 0 otherwise.
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unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const;
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};
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/// Return true if there is an instruction /after/ \p DefMI and before \p UseMI
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/// which either reads or clobbers NZCV.
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bool isNZCVTouchedInInstructionRange(const MachineInstr &DefMI,
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const MachineInstr &UseMI,
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const TargetRegisterInfo *TRI);
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/// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
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/// plus Offset. This is intended to be used from within the prolog/epilog
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/// insertion (PEI) pass, where a virtual scratch register may be allocated
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/// if necessary, to be replaced by the scavenger at the end of PEI.
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void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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StackOffset Offset, const TargetInstrInfo *TII,
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MachineInstr::MIFlag = MachineInstr::NoFlags,
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bool SetNZCV = false, bool NeedsWinCFI = false,
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bool *HasWinCFI = nullptr);
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/// rewriteAArch64FrameIndex - Rewrite MI to access 'Offset' bytes from the
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/// FP. Return false if the offset could not be handled directly in MI, and
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/// return the left-over portion by reference.
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bool rewriteAArch64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
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unsigned FrameReg, StackOffset &Offset,
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const AArch64InstrInfo *TII);
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/// Use to report the frame offset status in isAArch64FrameOffsetLegal.
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enum AArch64FrameOffsetStatus {
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AArch64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
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AArch64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
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AArch64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
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};
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/// Check if the @p Offset is a valid frame offset for @p MI.
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/// The returned value reports the validity of the frame offset for @p MI.
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/// It uses the values defined by AArch64FrameOffsetStatus for that.
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/// If result == AArch64FrameOffsetCannotUpdate, @p MI cannot be updated to
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/// use an offset.eq
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/// If result & AArch64FrameOffsetIsLegal, @p Offset can completely be
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/// rewritten in @p MI.
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/// If result & AArch64FrameOffsetCanUpdate, @p Offset contains the
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/// amount that is off the limit of the legal offset.
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/// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
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/// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
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/// If set, @p EmittableOffset contains the amount that can be set in @p MI
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/// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
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/// is a legal offset.
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int isAArch64FrameOffsetLegal(const MachineInstr &MI, StackOffset &Offset,
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bool *OutUseUnscaledOp = nullptr,
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unsigned *OutUnscaledOp = nullptr,
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int64_t *EmittableOffset = nullptr);
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static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; }
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static inline bool isCondBranchOpcode(int Opc) {
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switch (Opc) {
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case AArch64::Bcc:
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case AArch64::CBZW:
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case AArch64::CBZX:
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case AArch64::CBNZW:
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case AArch64::CBNZX:
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case AArch64::TBZW:
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case AArch64::TBZX:
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case AArch64::TBNZW:
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case AArch64::TBNZX:
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return true;
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default:
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return false;
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}
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}
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static inline bool isIndirectBranchOpcode(int Opc) {
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return Opc == AArch64::BR;
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}
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// struct TSFlags {
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#define TSFLAG_ELEMENT_SIZE_TYPE(X) (X) // 3-bits
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#define TSFLAG_DESTRUCTIVE_INST_TYPE(X) ((X) << 3) // 4-bit
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#define TSFLAG_FALSE_LANE_TYPE(X) ((X) << 7) // 2-bits
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// }
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namespace AArch64 {
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enum ElementSizeType {
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ElementSizeMask = TSFLAG_ELEMENT_SIZE_TYPE(0x7),
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ElementSizeNone = TSFLAG_ELEMENT_SIZE_TYPE(0x0),
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ElementSizeB = TSFLAG_ELEMENT_SIZE_TYPE(0x1),
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ElementSizeH = TSFLAG_ELEMENT_SIZE_TYPE(0x2),
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ElementSizeS = TSFLAG_ELEMENT_SIZE_TYPE(0x3),
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ElementSizeD = TSFLAG_ELEMENT_SIZE_TYPE(0x4),
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};
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enum DestructiveInstType {
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DestructiveInstTypeMask = TSFLAG_DESTRUCTIVE_INST_TYPE(0xf),
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NotDestructive = TSFLAG_DESTRUCTIVE_INST_TYPE(0x0),
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DestructiveOther = TSFLAG_DESTRUCTIVE_INST_TYPE(0x1),
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DestructiveUnary = TSFLAG_DESTRUCTIVE_INST_TYPE(0x2),
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DestructiveBinaryImm = TSFLAG_DESTRUCTIVE_INST_TYPE(0x3),
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DestructiveBinaryShImmUnpred = TSFLAG_DESTRUCTIVE_INST_TYPE(0x4),
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DestructiveBinary = TSFLAG_DESTRUCTIVE_INST_TYPE(0x5),
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DestructiveBinaryComm = TSFLAG_DESTRUCTIVE_INST_TYPE(0x6),
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DestructiveBinaryCommWithRev = TSFLAG_DESTRUCTIVE_INST_TYPE(0x7),
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DestructiveTernaryCommWithRev = TSFLAG_DESTRUCTIVE_INST_TYPE(0x8),
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};
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enum FalseLaneType {
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FalseLanesMask = TSFLAG_FALSE_LANE_TYPE(0x3),
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FalseLanesZero = TSFLAG_FALSE_LANE_TYPE(0x1),
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FalseLanesUndef = TSFLAG_FALSE_LANE_TYPE(0x2),
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};
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#undef TSFLAG_ELEMENT_SIZE_TYPE
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#undef TSFLAG_DESTRUCTIVE_INST_TYPE
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#undef TSFLAG_FALSE_LANE_TYPE
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int getSVEPseudoMap(uint16_t Opcode);
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int getSVERevInstr(uint16_t Opcode);
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int getSVEOrigInstr(uint16_t Opcode);
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}
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} // end namespace llvm
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#endif
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