Sam Parker 6ffd0e23b3 [CostModel] Unify getArithmeticInstrCost ... Add the remaining arithmetic opcodes into the generic implementation of getUserCost and then call this from getInstructionThroughput. Most of the backends have been modified to return the base implementation for cost kinds other RecipThroughput. The outlier here is AMDGPU which already uses getArithmeticInstrCost for all the cost kinds. This change means that most of the opcodes can be removed from that backends implementation of getUserCost. Differential Revision: https://reviews.llvm.org/D80992		2020-06-10 09:08:45 +01:00
..
AsmParser	[AArch64][AsmParser] Fix debug output in a few instructions	2020-06-09 09:02:59 +00:00
Disassembler
GISel	[AArch64] Move RegisterBankInfo.cpp/h to GISel.	2020-06-09 23:26:25 -07:00
MCTargetDesc	[AArch64] Support expression results as immediate values in mov	2020-06-08 17:57:20 -07:00
TargetInfo
Utils
AArch64.h	[MTE] Convert StackSafety into analysis	2020-06-02 16:08:14 -07:00
AArch64.td	[AARch64] Add Marvell ThunderX3T110 support	2020-05-13 16:58:51 -07:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp	[XRay] Change ARM/AArch64/powerpc64le to use version 2 sled (PC-relative address)	2020-04-24 08:35:43 -07:00
AArch64BranchTargets.cpp
AArch64CallingConvention.cpp	[Alignment][NFC] Migrate part of Arm/AArch64 backend	2020-06-08 07:15:37 +00:00
AArch64CallingConvention.h
AArch64CallingConvention.td	[AArch64] Treat x18 as callee-saved in functions with windows calling convention on non-windows OSes	2020-05-30 09:22:09 +03:00
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp	[AArch64] Fix CollectLOH creating an AdrpAdd LOH when there's a live used reg	2020-06-01 16:00:55 -07:00
AArch64Combine.td	[AArch64][GlobalISel] Select trn1 and trn2	2020-06-09 10:55:19 -07:00
AArch64CompressJumpTables.cpp
AArch64CondBrTuning.cpp	[AArch64CondBrTuning] Ignore debug insts when scanning for NZCV clobbers [10/14]	2020-04-22 17:03:40 -07:00
AArch64ConditionalCompares.cpp	MachineBasicBlock::updateTerminator now requires an explicit layout successor.	2020-06-06 22:30:51 -04:00
AArch64ConditionOptimizer.cpp	MachineBasicBlock::updateTerminator now requires an explicit layout successor.	2020-06-06 22:30:51 -04:00
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandImm.cpp
AArch64ExpandImm.h
AArch64ExpandPseudoInsts.cpp	[AArch64][SVE] Add support for spilling/filling ZPR2/3/4	2020-05-28 10:02:57 +00:00
AArch64FalkorHWPFFix.cpp
AArch64FastISel.cpp	[CodeGen] Use Align in MachineConstantPool.	2020-05-12 10:06:40 -07:00
AArch64FrameLowering.cpp	[AArch64] Treat x18 as callee-saved in functions with windows calling convention on non-windows OSes	2020-05-30 09:22:09 +03:00
AArch64FrameLowering.h
AArch64GenRegisterBankInfo.def
AArch64InstrAtomics.td
AArch64InstrFormats.td	[AArch64][BFloat] basic AArch64 bfloat support	2020-05-27 15:26:40 +01:00
AArch64InstrGISel.td	[AArch64][GlobalISel] Select trn1 and trn2	2020-06-09 10:55:19 -07:00
AArch64InstrInfo.cpp	[AMDGPU/MemOpsCluster] Let mem ops clustering logic also consider number of clustered bytes	2020-06-01 22:52:34 +05:30
AArch64InstrInfo.h	[AMDGPU/MemOpsCluster] Let mem ops clustering logic also consider number of clustered bytes	2020-06-01 22:52:34 +05:30
AArch64InstrInfo.td	[AArch64] Allow BTI mnemonics in the HINT space with BTI disabled	2020-06-09 19:57:02 +02:00
AArch64ISelDAGToDAG.cpp	[AArch64][SVE] Implement structured load intrinsics	2020-06-09 08:51:58 +00:00
AArch64ISelLowering.cpp	[AArch64] custom lowering for i128 popcount	2020-06-10 09:44:16 +04:00
AArch64ISelLowering.h	[Alignment][NFC] TargetLowering::allowsMisalignedMemoryAccesses	2020-06-09 10:17:42 +00:00
AArch64LoadStoreOptimizer.cpp	[AArch64] Fix ldst-opt of multiple disjunct subregs.	2020-06-08 20:18:24 +01:00
AArch64MachineFunctionInfo.cpp	MachineFunctionInfo for AArch64 in MIR	2020-04-17 15:16:59 -07:00
AArch64MachineFunctionInfo.h	[MachineOutliner] Annotation for outlined functions in AArch64	2020-04-20 13:33:31 -07:00
AArch64MacroFusion.cpp
AArch64MacroFusion.h
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PfmCounters.td
AArch64PromoteConstant.cpp	[AArch64] Don't promote constants with float ConstantExpr.	2020-05-13 23:31:47 +01:00
AArch64RedundantCopyElimination.cpp
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp	[AArch64] Treat x18 as callee-saved in functions with windows calling convention on non-windows OSes	2020-05-30 09:22:09 +03:00
AArch64RegisterInfo.h	[AArch64] Provide Darwin variants of most calling conventions	2020-05-20 16:03:48 -07:00
AArch64RegisterInfo.td	[AArch64][BFloat] basic AArch64 bfloat support	2020-05-27 15:26:40 +01:00
AArch64SchedA53.td	[AARch64] Add Marvell ThunderX3T110 support	2020-05-13 16:58:51 -07:00
AArch64SchedA57.td	[AARch64] Add Marvell ThunderX3T110 support	2020-05-13 16:58:51 -07:00
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td	[AARch64] Add Marvell ThunderX3T110 support	2020-05-13 16:58:51 -07:00
AArch64SchedExynosM3.td	[AARch64] Add Marvell ThunderX3T110 support	2020-05-13 16:58:51 -07:00
AArch64SchedExynosM4.td	[AARch64] Add Marvell ThunderX3T110 support	2020-05-13 16:58:51 -07:00
AArch64SchedExynosM5.td	[AARch64] Add Marvell ThunderX3T110 support	2020-05-13 16:58:51 -07:00
AArch64SchedFalkor.td	[AARch64] Add Marvell ThunderX3T110 support	2020-05-13 16:58:51 -07:00
AArch64SchedFalkorDetails.td
AArch64SchedKryo.td	[AARch64] Add Marvell ThunderX3T110 support	2020-05-13 16:58:51 -07:00
AArch64SchedKryoDetails.td
AArch64SchedPredExynos.td
AArch64SchedPredicates.td
AArch64SchedThunderX2T99.td	[AARch64] Add Marvell ThunderX3T110 support	2020-05-13 16:58:51 -07:00
AArch64SchedThunderX3T110.td	[AARch64] Add Marvell ThunderX3T110 support	2020-05-13 16:58:51 -07:00
AArch64SchedThunderX.td	[AARch64] Add Marvell ThunderX3T110 support	2020-05-13 16:58:51 -07:00
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64SIMDInstrOpt.cpp
AArch64SpeculationHardening.cpp
AArch64StackOffset.h
AArch64StackTagging.cpp	DomTreeUpdater.h - refine includes. NFC.	2020-06-07 16:57:48 +01:00
AArch64StackTaggingPreRA.cpp
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp	[AArch64] Move RegisterBankInfo.cpp/h to GISel.	2020-06-09 23:26:25 -07:00
AArch64Subtarget.h	[AARch64] Add Marvell ThunderX3T110 support	2020-05-13 16:58:51 -07:00
AArch64SVEInstrInfo.td	[llvm][SVE] IR intrinsic for LD1RO.	2020-06-03 13:57:16 +00:00
AArch64SystemOperands.td	[AArch64] Remove inexistent system register ERXTS_EL1	2020-04-29 16:43:48 +01:00
AArch64TargetMachine.cpp	[MTE] Move tagging in pipeline	2020-06-02 17:48:55 -07:00
AArch64TargetMachine.h	MachineFunctionInfo for AArch64 in MIR	2020-04-17 15:16:59 -07:00
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp	[CostModel] Unify getArithmeticInstrCost	2020-06-10 09:08:45 +01:00
AArch64TargetTransformInfo.h	[NFC][CostModel] Add TargetCostKind to relevant APIs	2020-05-05 10:35:54 +01:00
CMakeLists.txt	[AArch64] Move RegisterBankInfo.cpp/h to GISel.	2020-06-09 23:26:25 -07:00
LLVMBuild.txt
SVEInstrFormats.td	[llvm][SVE] IR intrinsic for LD1RO.	2020-06-03 13:57:16 +00:00
SVEIntrinsicOpts.cpp	[SVEIntrinsicOpts] NFC: Remove unused isReinterpretFromBool for no-assert builds	2020-04-21 09:49:22 +01:00