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a72e83c26e
For historic reasons, the behavior of .align differs between targets. Fortunately, there are alternatives, .p2align and .balign, which make the interpretation of the parameter explicit, and which behave consistently across targets. This patch teaches MC to use .p2align instead of .align, so that people reading code for multiple architectures don't have to remember which way each platform does its .align directive. Differential Revision: http://reviews.llvm.org/D16549 llvm-svn: 258750
264 lines
7.6 KiB
LLVM
264 lines
7.6 KiB
LLVM
; RUN: llc < %s -march=xcore | FileCheck %s
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; RUN: llc < %s -march=xcore -disable-fp-elim | FileCheck %s -check-prefix=CHECKFP
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; When using SP for small frames, we don't need any scratch registers (SR).
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; When using SP for large frames, we may need two scratch registers.
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; When using FP, for large or small frames, we may need one scratch register.
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; FP + small frame: spill FP+SR = entsp 2
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; CHECKFP-LABEL: f1
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; CHECKFP: entsp 2
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; CHECKFP-NEXT: stw r10, sp[1]
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; CHECKFP-NEXT: ldaw r10, sp[0]
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; CHECKFP: set sp, r10
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; CHECKFP-NEXT: ldw r10, sp[1]
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; CHECKFP-NEXT: retsp 2
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;
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; !FP + small frame: no spills = no stack adjustment needed
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; CHECK-LABEL: f1
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; CHECK: stw lr, sp[0]
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; CHECK: ldw lr, sp[0]
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; CHECK-NEXT: retsp 0
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define void @f1() nounwind {
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entry:
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tail call void asm sideeffect "", "~{lr}"() nounwind
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ret void
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}
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; FP + small frame: spill FP+SR+R0+LR = entsp 3 + extsp 1
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; CHECKFP-LABEL:f3
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; CHECKFP: entsp 3
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; CHECKFP-NEXT: stw r10, sp[1]
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; CHECKFP-NEXT: ldaw r10, sp[0]
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; CHECKFP-NEXT: stw [[REG:r[4-9]+]], r10[2]
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; CHECKFP-NEXT: mov [[REG]], r0
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; CHECKFP-NEXT: extsp 1
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; CHECKFP-NEXT: bl f2
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; CHECKFP-NEXT: ldaw sp, sp[1]
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; CHECKFP-NEXT: mov r0, [[REG]]
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; CHECKFP-NEXT: ldw [[REG]], r10[2]
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; CHECKFP-NEXT: set sp, r10
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; CHECKFP-NEXT: ldw r10, sp[1]
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; CHECKFP-NEXT: retsp 3
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;
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; !FP + small frame: spill R0+LR = entsp 2
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; CHECK-LABEL: f3
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; CHECK: entsp 2
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; CHECK-NEXT: stw [[REG:r[4-9]+]], sp[1]
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; CHECK-NEXT: mov [[REG]], r0
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; CHECK-NEXT: bl f2
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; CHECK-NEXT: mov r0, [[REG]]
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; CHECK-NEXT: ldw [[REG]], sp[1]
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; CHECK-NEXT: retsp 2
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declare void @f2()
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define i32 @f3(i32 %i) nounwind {
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entry:
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call void @f2()
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ret i32 %i
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}
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; FP + large frame: spill FP+SR = entsp 2 + 100000
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; CHECKFP-LABEL: f4
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; CHECKFP: entsp 65535
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_def_cfa_offset 262140
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_offset 15, 0
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; CHECKFP-NEXT: extsp 34467
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_def_cfa_offset 400008
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; CHECKFP-NEXT: stw r10, sp[1]
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_offset 10, -400004
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; CHECKFP-NEXT: ldaw r10, sp[0]
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_def_cfa_register 10
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; CHECKFP-NEXT: set sp, r10
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; CHECKFP-NEXT: ldw r10, sp[1]
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; CHECKFP-NEXT: ldaw sp, sp[65535]
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; CHECKFP-NEXT: retsp 34467
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;
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; !FP + large frame: spill SR+SR = entsp 2 + 100000
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; CHECK-LABEL: f4
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; CHECK: entsp 65535
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_def_cfa_offset 262140
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_offset 15, 0
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; CHECK-NEXT: extsp 34467
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_def_cfa_offset 400008
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; CHECK-NEXT: ldaw sp, sp[65535]
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; CHECK-NEXT: retsp 34467
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define void @f4() {
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entry:
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%0 = alloca [100000 x i32]
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ret void
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}
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; FP + large frame: spill FP+SR+R4+LR = entsp 3 + 200000 + extsp 1
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; CHECKFP: .section .cp.rodata.cst4,"aMc",@progbits,4
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; CHECKFP-NEXT: .p2align 2
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; CHECKFP-NEXT: .LCPI[[CNST0:[0-9_]+]]:
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; CHECKFP-NEXT: .long 200002
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; CHECKFP-NEXT: .LCPI[[CNST1:[0-9_]+]]:
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; CHECKFP-NEXT: .long 200001
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; CHECKFP-NEXT: .text
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; CHECKFP-LABEL: f6
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; CHECKFP: entsp 65535
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_def_cfa_offset 262140
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_offset 15, 0
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; CHECKFP-NEXT: extsp 65535
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_def_cfa_offset 524280
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; CHECKFP-NEXT: extsp 65535
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_def_cfa_offset 786420
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; CHECKFP-NEXT: extsp 3398
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_def_cfa_offset 800012
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; CHECKFP-NEXT: stw r10, sp[1]
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_offset 10, -800008
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; CHECKFP-NEXT: ldaw r10, sp[0]
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_def_cfa_register 10
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; CHECKFP-NEXT: ldw r1, cp[.LCPI[[CNST0]]]
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; CHECKFP-NEXT: stw [[REG:r[4-9]+]], r10[r1]
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; CHECKFP-NEXT: .Ltmp{{[0-9]+}}
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; CHECKFP-NEXT: .cfi_offset 4, -4
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; CHECKFP-NEXT: mov [[REG]], r0
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; CHECKFP-NEXT: extsp 1
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; CHECKFP-NEXT: ldaw r0, r10[2]
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; CHECKFP-NEXT: bl f5
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; CHECKFP-NEXT: ldaw sp, sp[1]
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; CHECKFP-NEXT: ldw r1, cp[.LCPI3_1]
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; CHECKFP-NEXT: ldaw r0, r10[r1]
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; CHECKFP-NEXT: extsp 1
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; CHECKFP-NEXT: bl f5
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; CHECKFP-NEXT: ldaw sp, sp[1]
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; CHECKFP-NEXT: mov r0, [[REG]]
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; CHECKFP-NEXT: ldw r1, cp[.LCPI[[CNST0]]]
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; CHECKFP-NEXT: ldw [[REG]], r10[r1]
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; CHECKFP-NEXT: set sp, r10
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; CHECKFP-NEXT: ldw r10, sp[1]
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; CHECKFP-NEXT: ldaw sp, sp[65535]
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; CHECKFP-NEXT: ldaw sp, sp[65535]
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; CHECKFP-NEXT: ldaw sp, sp[65535]
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; CHECKFP-NEXT: retsp 3398
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;
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; !FP + large frame: spill SR+SR+R4+LR = entsp 4 + 200000
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; CHECK: .section .cp.rodata.cst4,"aMc",@progbits,4
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: .LCPI[[CNST0:[0-9_]+]]:
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; CHECK-NEXT: .long 200003
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; CHECK-NEXT: .LCPI[[CNST1:[0-9_]+]]:
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; CHECK-NEXT: .long 200002
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; CHECK-NEXT: .text
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; CHECK-LABEL: f6
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; CHECK: entsp 65535
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_def_cfa_offset 262140
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_offset 15, 0
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; CHECK-NEXT: extsp 65535
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_def_cfa_offset 524280
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; CHECK-NEXT: extsp 65535
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_def_cfa_offset 786420
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; CHECK-NEXT: extsp 3399
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_def_cfa_offset 800016
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; CHECK-NEXT: ldaw r1, sp[0]
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; CHECK-NEXT: ldw r2, cp[.LCPI[[CNST0]]]
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; CHECK-NEXT: stw [[REG:r[4-9]+]], r1[r2]
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; CHECK-NEXT: .Ltmp{{[0-9]+}}
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; CHECK-NEXT: .cfi_offset 4, -4
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; CHECK-NEXT: mov [[REG]], r0
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; CHECK-NEXT: ldaw r0, sp[3]
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; CHECK-NEXT: bl f5
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; CHECK-NEXT: ldaw r0, sp[0]
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; CHECK-NEXT: ldw r1, cp[.LCPI[[CNST1]]]
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; CHECK-NEXT: ldaw r0, r0[r1]
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; CHECK-NEXT: bl f5
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; CHECK-NEXT: mov r0, [[REG]]
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; CHECK-NEXT: ldaw [[REG]], sp[0]
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; CHECK-NEXT: ldw r1, cp[.LCPI[[CNST0]]]
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; CHECK-NEXT: ldw [[REG]], [[REG]][r1]
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; CHECK-NEXT: ldaw sp, sp[65535]
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; CHECK-NEXT: ldaw sp, sp[65535]
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; CHECK-NEXT: ldaw sp, sp[65535]
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; CHECK-NEXT: retsp 3399
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declare void @f5(i32*)
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define i32 @f6(i32 %i) {
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entry:
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%0 = alloca [200000 x i32]
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%1 = getelementptr inbounds [200000 x i32], [200000 x i32]* %0, i32 0, i32 0
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call void @f5(i32* %1)
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%2 = getelementptr inbounds [200000 x i32], [200000 x i32]* %0, i32 0, i32 199999
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call void @f5(i32* %2)
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ret i32 %i
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}
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; FP + large frame: spill FP+SR+LR = entsp 2 + 256 + extsp 1
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; CHECKFP-LABEL:f8
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; CHECKFP: entsp 258
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; CHECKFP-NEXT: stw r10, sp[1]
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; CHECKFP-NEXT: ldaw r10, sp[0]
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; CHECKFP-NEXT: mkmsk [[REG:r[0-9]+]], 8
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; CHECKFP-NEXT: ldaw r0, r10{{\[}}[[REG]]{{\]}}
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; CHECKFP-NEXT: extsp 1
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; CHECKFP-NEXT: bl f5
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; CHECKFP-NEXT: ldaw sp, sp[1]
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; CHECKFP-NEXT: set sp, r10
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; CHECKFP-NEXT: ldw r10, sp[1]
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; CHECKFP-NEXT: retsp 258
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;
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; !FP + large frame: spill SR+SR+LR = entsp 3 + 256
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; CHECK-LABEL:f8
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; CHECK: entsp 257
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; CHECK-NEXT: ldaw r0, sp[254]
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; CHECK-NEXT: bl f5
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; CHECK-NEXT: retsp 257
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define void @f8() nounwind {
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entry:
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%0 = alloca [256 x i32]
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%1 = getelementptr inbounds [256 x i32], [256 x i32]* %0, i32 0, i32 253
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call void @f5(i32* %1)
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ret void
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}
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; FP + large frame: spill FP+SR+LR = entsp 2 + 32768 + extsp 1
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; CHECKFP-LABEL:f9
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; CHECKFP: entsp 32770
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; CHECKFP-NEXT: stw r10, sp[1]
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; CHECKFP-NEXT: ldaw r10, sp[0]
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; CHECKFP-NEXT: ldc [[REG:r[0-9]+]], 32767
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; CHECKFP-NEXT: ldaw r0, r10{{\[}}[[REG]]{{\]}}
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; CHECKFP-NEXT: extsp 1
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; CHECKFP-NEXT: bl f5
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; CHECKFP-NEXT: ldaw sp, sp[1]
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; CHECKFP-NEXT: set sp, r10
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; CHECKFP-NEXT: ldw r10, sp[1]
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; CHECKFP-NEXT: retsp 32770
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;
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; !FP + large frame: spill SR+SR+LR = entsp 3 + 32768
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; CHECK-LABEL:f9
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; CHECK: entsp 32771
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; CHECK-NEXT: ldaw r0, sp[32768]
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; CHECK-NEXT: bl f5
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; CHECK-NEXT: retsp 32771
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define void @f9() nounwind {
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entry:
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%0 = alloca [32768 x i32]
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%1 = getelementptr inbounds [32768 x i32], [32768 x i32]* %0, i32 0, i32 32765
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call void @f5(i32* %1)
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ret void
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}
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