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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 12:02:58 +02:00
llvm-mirror/test/CodeGen
Duncan P. N. Exon Smith 73ce6dbb2b Revert "Masked Vector Load and Store Intrinsics."
This reverts commit r222632 (and follow-up r222636), which caused a host
of LNT failures on an internal bot.  I'll respond to the commit on the
list with a reproduction of one of the failures.

Conflicts:
	lib/Target/X86/X86TargetTransformInfo.cpp

llvm-svn: 222936
2014-11-28 21:29:14 +00:00
..
AArch64 AArch64: treat [N x Ty] as a block during procedure calls. 2014-11-27 21:02:42 +00:00
ARM Stop uppercasing build attribute data. 2014-11-27 12:13:56 +00:00
CPP
Generic Revert "Revert "DI: Fold constant arguments into a single MDString"" 2014-10-03 20:01:09 +00:00
Hexagon Handle ctor/init_array initialization. 2014-11-03 14:56:05 +00:00
Inputs Revert "Revert "DI: Fold constant arguments into a single MDString"" 2014-10-03 20:01:09 +00:00
Mips [mips][micromips] Use call instructions with short delay slots 2014-11-25 10:50:00 +00:00
MSP430
NVPTX [NVPTX] Add NVPTXLowerStructArgs pass 2014-11-05 18:19:30 +00:00
PowerPC [PowerPC] Implement combineRepeatedFPDivisors 2014-11-24 23:45:21 +00:00
R600 R600: Fix extloads of i1 on R600/Evergreen 2014-11-23 02:57:54 +00:00
SPARC Add back tests for empty function in SPARC and PowerPC. 2014-09-15 22:11:07 +00:00
SystemZ
Thumb [Thumb1] Re-write emitThumbRegPlusImmediate 2014-11-17 11:18:10 +00:00
Thumb2 ARM: allow constpool entry to be moved to the user's block in all cases. 2014-11-13 17:58:53 +00:00
X86 Revert "Masked Vector Load and Store Intrinsics." 2014-11-28 21:29:14 +00:00
XCore Fix a bit of confusion about .set and produce more readable assembly. 2014-10-21 01:17:30 +00:00