Simon Pilgrim 70f5e23577 [X86][AVX] Add test case for PR51281 ... (cherry picked from commit 6569b7f90239b5932465a1c6936632b4a9527d66)		2021-08-02 20:05:12 -07:00
..
AArch64	[DAGCombiner] don't try to partially reduce add-with-overflow ops	2021-08-02 13:52:48 -07:00
AMDGPU	AMDGPU/GlobalISel: Fix selecting G_SEXTLOAD/G_ZEXTLOAD pre-gfx9	2021-07-27 15:56:42 -04:00
ARC
ARM	[Local] Do not introduce a new llvm.trap before unreachable	2021-07-26 23:33:36 -05:00
AVR	[AVR] Only support sp, r0 and r1 in llvm.read_register	2021-07-24 14:03:27 +02:00
BPF
Generic	[PowerPC] Add pwr7 and pwr10 support to IBM MASSV pass on AIX	2021-07-26 23:21:38 +00:00
Hexagon	[Hexagon] Fix resetting dead registers in DBG_VALUE_LISTs	2021-07-27 18:36:28 -05:00
Inputs
Lanai
M68k
Mips	[llvm][sve] Lowering for VLS truncating stores	2021-07-23 14:04:55 +01:00
MIR
MSP430
NVPTX
PowerPC	[PowerPC] Turn deprecated altivec prefetch instrs to nops on AIX	2021-07-27 15:50:02 -05:00
RISCV	[RISCV] Restrict performANY_EXTENDCombine to prevent an infinite loop.	2021-08-02 11:31:08 -07:00
SPARC
SystemZ	[SystemZ][z/OS] Initial code to generate assembly files on z/OS	2021-07-27 11:29:15 -04:00
Thumb
Thumb2	[ARM] Implement isLoad/StoreFromStackSlot for MVE stack stores accesses	2021-07-27 09:11:58 +01:00
VE
WebAssembly	[WebAssembly] Codegen for extmul SIMD instructions	2021-07-27 08:41:30 -07:00
WinCFGuard
WinEH
X86	[X86][AVX] Add test case for PR51281	2021-08-02 20:05:12 -07:00
XCore