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13a750213e
We already have reassociation code for Adds and Ors separately in DAG combiner, this adds it for the combination of the two where Ors act like Adds. It reassociates (add (or (x, c), y) -> (add (add (x, y), c)) where we know that the Ors operands have no common bits set, and the Or has one use. Differential Revision: https://reviews.llvm.org/D104765
284 lines
8.2 KiB
LLVM
284 lines
8.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv6m-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-T1
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; RUN: llc -mtriple=thumbv7m-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-T2
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; RUN: llc -mtriple=armv7a-none-eabi %s -o - | FileCheck %s --check-prefixes=CHECK-A
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define i32 @test_add_i3(i1 %tst, i32 %a, i32 %b) {
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; CHECK-T1-LABEL: test_add_i3:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: .save {r4, lr}
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; CHECK-T1-NEXT: push {r4, lr}
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; CHECK-T1-NEXT: lsls r0, r0, #31
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; CHECK-T1-NEXT: bne .LBB0_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: movs r0, #3
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; CHECK-T1-NEXT: bics r2, r0
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; CHECK-T1-NEXT: mov r4, r2
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; CHECK-T1-NEXT: b .LBB0_3
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; CHECK-T1-NEXT: .LBB0_2:
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; CHECK-T1-NEXT: mov r4, r1
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; CHECK-T1-NEXT: movs r0, #6
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; CHECK-T1-NEXT: bics r4, r0
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; CHECK-T1-NEXT: .LBB0_3:
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; CHECK-T1-NEXT: mov r0, r4
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; CHECK-T1-NEXT: bl foo
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; CHECK-T1-NEXT: adds r0, r4, #2
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; CHECK-T1-NEXT: pop {r4, pc}
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;
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; CHECK-T2-LABEL: test_add_i3:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: .save {r4, lr}
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; CHECK-T2-NEXT: push {r4, lr}
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; CHECK-T2-NEXT: lsls r0, r0, #31
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; CHECK-T2-NEXT: bic r4, r2, #3
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: bicne r4, r1, #6
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; CHECK-T2-NEXT: mov r0, r4
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; CHECK-T2-NEXT: bl foo
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; CHECK-T2-NEXT: adds r0, r4, #2
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; CHECK-T2-NEXT: pop {r4, pc}
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;
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; CHECK-A-LABEL: test_add_i3:
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; CHECK-A: @ %bb.0:
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; CHECK-A-NEXT: .save {r4, lr}
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; CHECK-A-NEXT: push {r4, lr}
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; CHECK-A-NEXT: bic r4, r2, #3
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; CHECK-A-NEXT: tst r0, #1
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; CHECK-A-NEXT: bicne r4, r1, #6
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; CHECK-A-NEXT: mov r0, r4
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; CHECK-A-NEXT: bl foo
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; CHECK-A-NEXT: orr r0, r4, #2
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; CHECK-A-NEXT: pop {r4, pc}
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%tmp = and i32 %a, -7
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%tmp1 = and i32 %b, -4
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%int = select i1 %tst, i32 %tmp, i32 %tmp1
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; Call to force %int into a register that isn't r0 so using the i3 form is a
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; good idea.
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call void @foo(i32 %int)
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%res = or i32 %int, 2
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ret i32 %res
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}
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define i32 @test_add_i8(i32 %a, i32 %b, i1 %tst) {
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; CHECK-T1-LABEL: test_add_i8:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: lsls r2, r2, #31
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; CHECK-T1-NEXT: bne .LBB1_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: ldr r0, .LCPI1_0
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; CHECK-T1-NEXT: ands r1, r0
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; CHECK-T1-NEXT: mov r0, r1
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; CHECK-T1-NEXT: adds r0, #12
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; CHECK-T1-NEXT: bx lr
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; CHECK-T1-NEXT: .LBB1_2:
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; CHECK-T1-NEXT: movs r1, #255
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; CHECK-T1-NEXT: bics r0, r1
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; CHECK-T1-NEXT: adds r0, #12
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; CHECK-T1-NEXT: bx lr
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; CHECK-T1-NEXT: .p2align 2
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; CHECK-T1-NEXT: @ %bb.3:
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; CHECK-T1-NEXT: .LCPI1_0:
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; CHECK-T1-NEXT: .long 4294966784 @ 0xfffffe00
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;
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; CHECK-T2-LABEL: test_add_i8:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: movw r3, #511
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; CHECK-T2-NEXT: bics r1, r3
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; CHECK-T2-NEXT: lsls r2, r2, #31
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: bicne r1, r0, #255
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; CHECK-T2-NEXT: add.w r0, r1, #12
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-A-LABEL: test_add_i8:
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; CHECK-A: @ %bb.0:
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; CHECK-A-NEXT: bfc r1, #0, #9
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; CHECK-A-NEXT: tst r2, #1
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; CHECK-A-NEXT: bicne r1, r0, #255
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; CHECK-A-NEXT: orr r0, r1, #12
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; CHECK-A-NEXT: bx lr
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%tmp = and i32 %a, -256
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%tmp1 = and i32 %b, -512
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%int = select i1 %tst, i32 %tmp, i32 %tmp1
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%res = or i32 %int, 12
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ret i32 %res
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}
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define i32 @test_add_i12(i32 %a, i32 %b, i1 %tst) {
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; CHECK-T1-LABEL: test_add_i12:
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; CHECK-T1: @ %bb.0:
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; CHECK-T1-NEXT: lsls r2, r2, #31
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; CHECK-T1-NEXT: bne .LBB2_2
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; CHECK-T1-NEXT: @ %bb.1:
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; CHECK-T1-NEXT: ldr r0, .LCPI2_1
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; CHECK-T1-NEXT: ands r1, r0
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; CHECK-T1-NEXT: mov r0, r1
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; CHECK-T1-NEXT: b .LBB2_3
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; CHECK-T1-NEXT: .LBB2_2:
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; CHECK-T1-NEXT: ldr r1, .LCPI2_0
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; CHECK-T1-NEXT: ands r0, r1
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; CHECK-T1-NEXT: .LBB2_3:
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; CHECK-T1-NEXT: ldr r1, .LCPI2_2
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; CHECK-T1-NEXT: adds r0, r0, r1
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; CHECK-T1-NEXT: bx lr
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; CHECK-T1-NEXT: .p2align 2
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; CHECK-T1-NEXT: @ %bb.4:
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; CHECK-T1-NEXT: .LCPI2_0:
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; CHECK-T1-NEXT: .long 4294963200 @ 0xfffff000
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; CHECK-T1-NEXT: .LCPI2_1:
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; CHECK-T1-NEXT: .long 4294959104 @ 0xffffe000
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; CHECK-T1-NEXT: .LCPI2_2:
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; CHECK-T1-NEXT: .long 854 @ 0x356
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;
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; CHECK-T2-LABEL: test_add_i12:
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; CHECK-T2: @ %bb.0:
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; CHECK-T2-NEXT: movw r3, #8191
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; CHECK-T2-NEXT: bics r1, r3
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; CHECK-T2-NEXT: movw r12, #4095
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; CHECK-T2-NEXT: lsls r2, r2, #31
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; CHECK-T2-NEXT: it ne
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; CHECK-T2-NEXT: bicne.w r1, r0, r12
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; CHECK-T2-NEXT: addw r0, r1, #854
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-A-LABEL: test_add_i12:
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; CHECK-A: @ %bb.0:
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; CHECK-A-NEXT: bfc r1, #0, #13
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; CHECK-A-NEXT: bfc r0, #0, #12
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; CHECK-A-NEXT: tst r2, #1
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; CHECK-A-NEXT: moveq r0, r1
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; CHECK-A-NEXT: movw r1, #854
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; CHECK-A-NEXT: orr r0, r0, r1
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; CHECK-A-NEXT: bx lr
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%tmp = and i32 %a, -4096
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%tmp1 = and i32 %b, -8192
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%int = select i1 %tst, i32 %tmp, i32 %tmp1
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%res = or i32 %int, 854
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ret i32 %res
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}
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define i32 @oradd(i32 %i, i32 %y) {
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; CHECK-T1-LABEL: oradd:
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; CHECK-T1: @ %bb.0: @ %entry
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; CHECK-T1-NEXT: lsls r0, r0, #1
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; CHECK-T1-NEXT: adds r0, r1, r0
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; CHECK-T1-NEXT: adds r0, r0, #1
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: oradd:
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; CHECK-T2: @ %bb.0: @ %entry
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; CHECK-T2-NEXT: add.w r0, r1, r0, lsl #1
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; CHECK-T2-NEXT: adds r0, #1
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-A-LABEL: oradd:
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; CHECK-A: @ %bb.0: @ %entry
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; CHECK-A-NEXT: add r0, r1, r0, lsl #1
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; CHECK-A-NEXT: add r0, r0, #1
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; CHECK-A-NEXT: bx lr
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entry:
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%mul = shl i32 %i, 1
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%or = or i32 %mul, 1
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%add = add i32 %or, %y
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ret i32 %add
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}
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define i32 @orgep(i32 %i, i32* %x, i32* %y) {
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; CHECK-T1-LABEL: orgep:
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; CHECK-T1: @ %bb.0: @ %entry
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; CHECK-T1-NEXT: lsls r0, r0, #3
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; CHECK-T1-NEXT: adds r0, r1, r0
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; CHECK-T1-NEXT: ldr r0, [r0, #4]
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: orgep:
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; CHECK-T2: @ %bb.0: @ %entry
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; CHECK-T2-NEXT: add.w r0, r1, r0, lsl #3
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; CHECK-T2-NEXT: ldr r0, [r0, #4]
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-A-LABEL: orgep:
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; CHECK-A: @ %bb.0: @ %entry
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; CHECK-A-NEXT: add r0, r1, r0, lsl #3
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; CHECK-A-NEXT: ldr r0, [r0, #4]
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; CHECK-A-NEXT: bx lr
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entry:
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%mul = shl i32 %i, 1
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%add = or i32 %mul, 1
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%arrayidx = getelementptr inbounds i32, i32* %x, i32 %add
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%0 = load i32, i32* %arrayidx, align 8
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ret i32 %0
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}
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define i32 @orgeps(i32 %i, i32* %x, i32* %y) {
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; CHECK-T1-LABEL: orgeps:
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; CHECK-T1: @ %bb.0: @ %entry
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; CHECK-T1-NEXT: lsls r0, r0, #3
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; CHECK-T1-NEXT: adds r0, r1, r0
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; CHECK-T1-NEXT: ldr r1, [r0, #4]
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; CHECK-T1-NEXT: ldr r0, [r0, #8]
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; CHECK-T1-NEXT: adds r0, r0, r1
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: orgeps:
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; CHECK-T2: @ %bb.0: @ %entry
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; CHECK-T2-NEXT: add.w r0, r1, r0, lsl #3
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; CHECK-T2-NEXT: ldrd r0, r1, [r0, #4]
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; CHECK-T2-NEXT: add r0, r1
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-A-LABEL: orgeps:
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; CHECK-A: @ %bb.0: @ %entry
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; CHECK-A-NEXT: add r0, r1, r0, lsl #3
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; CHECK-A-NEXT: ldrd r0, r1, [r0, #4]
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; CHECK-A-NEXT: add r0, r1, r0
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; CHECK-A-NEXT: bx lr
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entry:
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%mul = shl i32 %i, 1
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%add = or i32 %mul, 1
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%arrayidx = getelementptr inbounds i32, i32* %x, i32 %add
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%0 = load i32, i32* %arrayidx, align 8
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%add2 = add i32 %mul, 2
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%arrayidx3 = getelementptr inbounds i32, i32* %x, i32 %add2
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%1 = load i32, i32* %arrayidx3, align 8
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%add4 = add i32 %1, %0
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ret i32 %add4
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}
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define i32 @multiuse(i32 %i, i32* %x, i32* %y) {
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; CHECK-T1-LABEL: multiuse:
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; CHECK-T1: @ %bb.0: @ %entry
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; CHECK-T1-NEXT: lsls r0, r0, #1
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; CHECK-T1-NEXT: adds r0, r0, #1
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; CHECK-T1-NEXT: lsls r2, r0, #2
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; CHECK-T1-NEXT: ldr r1, [r1, r2]
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; CHECK-T1-NEXT: adds r0, r0, r1
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; CHECK-T1-NEXT: bx lr
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;
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; CHECK-T2-LABEL: multiuse:
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; CHECK-T2: @ %bb.0: @ %entry
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; CHECK-T2-NEXT: lsls r0, r0, #1
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; CHECK-T2-NEXT: adds r0, #1
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; CHECK-T2-NEXT: ldr.w r1, [r1, r0, lsl #2]
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; CHECK-T2-NEXT: add r0, r1
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; CHECK-T2-NEXT: bx lr
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;
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; CHECK-A-LABEL: multiuse:
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; CHECK-A: @ %bb.0: @ %entry
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; CHECK-A-NEXT: mov r2, #1
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; CHECK-A-NEXT: orr r0, r2, r0, lsl #1
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; CHECK-A-NEXT: ldr r1, [r1, r0, lsl #2]
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; CHECK-A-NEXT: add r0, r0, r1
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; CHECK-A-NEXT: bx lr
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entry:
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%mul = shl i32 %i, 1
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%add = or i32 %mul, 1
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%arrayidx = getelementptr inbounds i32, i32* %x, i32 %add
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%0 = load i32, i32* %arrayidx, align 8
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%r = add i32 %add, %0
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ret i32 %r
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}
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declare void @foo(i32)
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