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29b969dda5
These features (fairly) recently got split out into their own feature, so we should make CodeGen use them when available. The main change here is that the check used to be based on the triple, but now it's based on CPU features. llvm-svn: 349355
141 lines
3.9 KiB
LLVM
141 lines
3.9 KiB
LLVM
; RUN: llc -mtriple=thumbv7-none-eabi -mcpu=cortex-m33 -verify-machineinstrs -o - %s | FileCheck %s
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define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
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; CHECK-LABEL: test_atomic_load_add_i8:
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%old = atomicrmw add i8* @var8, i8 %offset seq_cst
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; CHECK-NOT: dmb
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; CHECK-NOT: mcr
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; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8
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; CHECK: movt r[[ADDR]], :upper16:var8
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; CHECK: .LBB{{[0-9]+}}_1:
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; CHECK: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]]
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; r0 below is a reasonable guess but could change: it certainly comes into the
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; function there.
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; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0
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; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
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; CHECK-NOT: dmb
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; CHECK-NOT: mcr
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; CHECK: mov r0, r[[OLD]]
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ret i8 %old
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}
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define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
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; CHECK-LABEL: test_atomic_load_add_i16:
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%old = atomicrmw add i16* @var16, i16 %offset acquire
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; CHECK-NOT: dmb
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; CHECK-NOT: mcr
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; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
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; CHECK: movt r[[ADDR]], :upper16:var16
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; CHECK: .LBB{{[0-9]+}}_1:
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; CHECK: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]]
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; r0 below is a reasonable guess but could change: it certainly comes into the
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; function there.
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; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0
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; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
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; CHECK-NOT: dmb
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; CHECK-NOT: mcr
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; CHECK: mov r0, r[[OLD]]
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ret i16 %old
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}
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define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
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; CHECK-LABEL: test_atomic_load_add_i32:
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%old = atomicrmw add i32* @var32, i32 %offset release
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; CHECK-NOT: dmb
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; CHECK-NOT: mcr
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; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32
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; CHECK: movt r[[ADDR]], :upper16:var32
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; CHECK: .LBB{{[0-9]+}}_1:
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; CHECK: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]]
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; r0 below is a reasonable guess but could change: it certainly comes into the
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; function there.
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; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0
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; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]]
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; CHECK-NEXT: cmp [[STATUS]], #0
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; CHECK-NEXT: bne .LBB{{[0-9]+}}_1
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; CHECK-NOT: dmb
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; CHECK-NOT: mcr
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; CHECK: mov r0, r[[OLD]]
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ret i32 %old
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}
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define void @test_atomic_load_add_i64(i64 %offset) nounwind {
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; CHECK-LABEL: test_atomic_load_add_i64:
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; CHECK: bl __sync_fetch_and_add_8
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%old = atomicrmw add i64* @var64, i64 %offset monotonic
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store i64 %old, i64* @var64
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ret void
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}
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define i8 @test_load_acquire_i8(i8* %ptr) {
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; CHECK-LABEL: test_load_acquire_i8:
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; CHECK: ldab r0, [r0]
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%val = load atomic i8, i8* %ptr seq_cst, align 1
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ret i8 %val
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}
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define i16 @test_load_acquire_i16(i16* %ptr) {
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; CHECK-LABEL: test_load_acquire_i16:
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; CHECK: ldah r0, [r0]
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%val = load atomic i16, i16* %ptr acquire, align 2
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ret i16 %val
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}
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define i32 @test_load_acquire_i32(i32* %ptr) {
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; CHECK-LABEL: test_load_acquire_i32:
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; CHECK: lda r0, [r0]
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%val = load atomic i32, i32* %ptr acquire, align 4
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ret i32 %val
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}
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define i64 @test_load_acquire_i64(i64* %ptr) {
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; CHECK-LABEL: test_load_acquire_i64:
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; CHECK: bl __atomic_load
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%val = load atomic i64, i64* %ptr acquire, align 4
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ret i64 %val
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}
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define void @test_store_release_i8(i8 %val, i8* %ptr) {
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; CHECK-LABEL: test_store_release_i8:
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; CHECK: stlb r0, [r1]
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store atomic i8 %val, i8* %ptr seq_cst, align 1
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ret void
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}
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define void @test_store_release_i16(i16 %val, i16* %ptr) {
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; CHECK-LABEL: test_store_release_i16:
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; CHECK: stlh r0, [r1]
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store atomic i16 %val, i16* %ptr release, align 2
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ret void
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}
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define void @test_store_release_i32(i32 %val, i32* %ptr) {
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; CHECK-LABEL: test_store_release_i32:
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; CHECK: stl r0, [r1]
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store atomic i32 %val, i32* %ptr seq_cst, align 4
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ret void
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}
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define void @test_store_release_i64(i64 %val, i64* %ptr) {
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; CHECK-LABEL: test_store_release_i64:
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; CHECK: bl __atomic_store
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store atomic i64 %val, i64* %ptr seq_cst, align 4
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ret void
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}
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@var8 = global i8 0
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@var16 = global i16 0
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@var32 = global i32 0
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@var64 = global i64 0
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