mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-22 18:54:02 +01:00
14bad468ca
This patch is part of a series implementing the Bfloat16 extension of the Armv8.6-a architecture, as detailed here: https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/arm-architecture-developments-armv8-6-a Specifically it adds intrinsic support in clang and llvm for Arm and AArch64. The bfloat type, and its properties are specified in the Arm Architecture Reference Manual: https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile The following people contributed to this patch: - Alexandros Lamprineas - Luke Cheeseman - Mikhail Maltsev - Momchil Velikov - Luke Geeson Differential Revision: https://reviews.llvm.org/D80928
57 lines
1.9 KiB
LLVM
57 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc < %s -verify-machineinstrs -mtriple=armv8.6a-arm-none-eabi -mattr=+neon,+bf16,+fullfp16 | FileCheck %s
|
|
|
|
declare bfloat @llvm.arm.neon.vcvtbfp2bf(float)
|
|
|
|
; Hard float ABI
|
|
declare <4 x bfloat> @llvm.arm.neon.vcvtfp2bf.v4bf16(<4 x float>)
|
|
|
|
define arm_aapcs_vfpcc <4 x bfloat> @test_vcvt_bf16_f32_hardfp(<4 x float> %a) {
|
|
; CHECK-LABEL: test_vcvt_bf16_f32_hardfp:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vcvt.bf16.f32 d0, q0
|
|
; CHECK-NEXT: bx lr
|
|
entry:
|
|
%vcvtfp2bf1.i.i = call <4 x bfloat> @llvm.arm.neon.vcvtfp2bf.v4bf16(<4 x float> %a)
|
|
ret <4 x bfloat> %vcvtfp2bf1.i.i
|
|
}
|
|
|
|
define arm_aapcs_vfpcc bfloat @test_vcvth_bf16_f32_hardfp(float %a) {
|
|
; CHECK-LABEL: test_vcvth_bf16_f32_hardfp:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vcvtb.bf16.f32 s0, s0
|
|
; CHECK-NEXT: bx lr
|
|
entry:
|
|
%vcvtbfp2bf.i = call bfloat @llvm.arm.neon.vcvtbfp2bf(float %a)
|
|
ret bfloat %vcvtbfp2bf.i
|
|
}
|
|
|
|
; Soft float ABI
|
|
declare <4 x i16> @llvm.arm.neon.vcvtfp2bf.v4i16(<4 x float>)
|
|
|
|
define <2 x i32> @test_vcvt_bf16_f32_softfp(<4 x float> %a) {
|
|
; CHECK-LABEL: test_vcvt_bf16_f32_softfp:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vmov d17, r2, r3
|
|
; CHECK-NEXT: vmov d16, r0, r1
|
|
; CHECK-NEXT: vcvt.bf16.f32 d16, q8
|
|
; CHECK-NEXT: vmov r0, r1, d16
|
|
; CHECK-NEXT: bx lr
|
|
entry:
|
|
%vcvtfp2bf1.i.i = call <4 x i16> @llvm.arm.neon.vcvtfp2bf.v4i16(<4 x float> %a)
|
|
%.cast = bitcast <4 x i16> %vcvtfp2bf1.i.i to <2 x i32>
|
|
ret <2 x i32> %.cast
|
|
}
|
|
|
|
define bfloat @test_vcvth_bf16_f32_softfp(float %a) #1 {
|
|
; CHECK-LABEL: test_vcvth_bf16_f32_softfp:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vmov s0, r0
|
|
; CHECK-NEXT: vcvtb.bf16.f32 s0, s0
|
|
; CHECK-NEXT: vmov r0, s0
|
|
; CHECK-NEXT: bx lr
|
|
entry:
|
|
%vcvtbfp2bf.i = call bfloat @llvm.arm.neon.vcvtbfp2bf(float %a) #3
|
|
ret bfloat %vcvtbfp2bf.i
|
|
}
|