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7dcf1654f8
Based ontop of D104598, which is a NFCI-ish refactoring. Here, a restriction, that only empty blocks can be merged, is lifted. Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D104597
96 lines
3.0 KiB
LLVM
96 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false | FileCheck %s
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; RUN: llc < %s -mtriple thumbv7s-apple-darwin -asm-verbose=false -stop-after=if-converter | FileCheck --check-prefix=CHECK-PROB %s
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declare i32 @foo(i32)
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declare i8* @bar(i32, i8*, i8*)
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; Verify that we don't try to iteratively re-ifconvert a block with a
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; (predicated) indirectbr terminator.
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; If we do, we would ignore its fallthrough successor.
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; CHECK-PROB: bb.0{{[0-9a-zA-Z.]*}}:
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; CHECK-PROB: successors: %bb.1(0x40000000), %bb.3(0x20000000), %bb.4(0x20000000)
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; CHECK-PROB: bb.2{{[0-9a-zA-Z.]*}}:
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; CHECK-PROB: successors: %bb.3(0x40000000), %bb.4(0x40000000)
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define i32 @test(i32 %a, i32 %a2, i32* %p, i32* %p2) "frame-pointer"="all" {
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; CHECK-LABEL: test:
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; CHECK: push {r4, r5, r6, r7, lr}
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; CHECK-NEXT: add r7, sp, #12
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; CHECK-NEXT: push.w {r8, r10, r11}
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; CHECK-NEXT: str r3, [sp, #-4]!
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; CHECK-NEXT: mov r11, r2
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; CHECK-NEXT: mov r4, r1
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; CHECK-NEXT: mov r5, r0
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; CHECK-NEXT: ldr r6, LCPI0_0
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; CHECK-NEXT: LPC0_1:
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; CHECK-NEXT: add r6, pc
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; CHECK-NEXT: ldr.w r8, LCPI0_1
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; CHECK-NEXT: LPC0_0:
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; CHECK-NEXT: add r8, pc
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; CHECK-NEXT: movs r0, #1
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; CHECK-NEXT: mov r1, r6
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; CHECK-NEXT: mov r2, r8
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; CHECK-NEXT: bl _bar
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; CHECK-NEXT: mov r10, r0
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; CHECK-NEXT: movs r0, #2
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; CHECK-NEXT: mov r1, r6
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; CHECK-NEXT: mov r2, r8
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; CHECK-NEXT: bl _bar
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; CHECK-NEXT: movs r0, #3
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; CHECK-NEXT: mov r1, r6
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; CHECK-NEXT: mov r2, r8
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; CHECK-NEXT: bl _bar
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; CHECK-NEXT: cmp r5, #21
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; CHECK-NEXT: itttt eq
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; CHECK-NEXT: moveq r1, r0
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; CHECK-NEXT: streq.w r5, [r11]
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; CHECK-NEXT: movweq r0, #1234
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; CHECK-NEXT: moveq pc, r1
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; CHECK-NEXT: LBB0_1:
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; CHECK-NEXT: cmp r4, #42
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; CHECK-NEXT: beq LBB0_4
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; CHECK-NEXT: ldr r0, [sp]
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; CHECK-NEXT: str r5, [r0]
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; CHECK-NEXT: movw r0, #1234
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; CHECK-NEXT: mov pc, r10
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; CHECK-NEXT: Ltmp0:
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; CHECK-NEXT: LBB0_3:
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; CHECK-NEXT: movw r0, #4567
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; CHECK-NEXT: b LBB0_5
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; CHECK-NEXT: LBB0_4:
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; CHECK-NEXT: movw r0, #1234
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; CHECK-NEXT: Ltmp1:
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; CHECK-NEXT: LBB0_5:
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; CHECK-NEXT: bl _foo
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; CHECK-NEXT: add sp, #4
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; CHECK-NEXT: pop.w {r8, r10, r11}
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; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
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; CHECK-NEXT: .p2align 2
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entry:
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%dst1 = call i8* @bar(i32 1, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2))
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%dst2 = call i8* @bar(i32 2, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2))
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%dst3 = call i8* @bar(i32 3, i8* blockaddress(@test, %bb1), i8* blockaddress(@test, %bb2))
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%cc1 = icmp eq i32 %a, 21
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br i1 %cc1, label %cc1t, label %cc1f
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cc1t:
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store i32 %a, i32* %p
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indirectbr i8* %dst3, [label %bb1, label %bb2]
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cc1f:
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%cc2 = icmp ne i32 %a2, 42
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br i1 %cc2, label %cc2t, label %bb1
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cc2t:
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store i32 %a, i32* %p2
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indirectbr i8* %dst1, [label %bb1, label %bb2]
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bb1:
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%ret_bb1 = call i32 @foo(i32 1234)
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ret i32 %ret_bb1
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bb2:
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%ret_bb2 = call i32 @foo(i32 4567)
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ret i32 %ret_bb2
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}
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