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c28d8cf19b
This commit removes the artificial types <512 x i1> and <1024 x i1>
from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal on
Hexagon.
It may cause existing bitcode files to become invalid.
* Converting between vector predicates and vector registers must be
done explicitly via vandvrt/vandqrt instructions (their intrinsics),
i.e. (for 64-byte mode):
%Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1)
%V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1)
The conversion intrinsics are:
declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32)
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32)
They are all pure.
* Vector predicate values cannot be loaded/stored directly. This directly
reflects the architecture restriction. Loading and storing or vector
predicates must be done indirectly via vector registers and explicit
conversions via vandvrt/vandqrt instructions.
37 lines
1.2 KiB
LLVM
37 lines
1.2 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; REQUIRES: asserts
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; Hexagon early if-conversion used to crash on this testcase due to not
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; recognizing vector predicate registers.
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target triple = "hexagon"
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; Check that the early if-conversion has not happened.
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; CHECK-LABEL: fred
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; CHECK: q{{[0-3]}} = not
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; CHECK: LBB
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; CHECK: if (q{{[0-3]}}) vmem
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define void @fred(i32 %a0) #0 {
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b1:
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%v2 = tail call <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32 %a0) #2
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br i1 undef, label %b3, label %b5
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b3: ; preds = %b1
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%v4 = tail call <128 x i1> @llvm.hexagon.V6.pred.not.128B(<128 x i1> %v2) #2
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br label %b5
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b5: ; preds = %b3, %b1
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%v6 = phi <128 x i1> [ %v4, %b3 ], [ %v2, %b1 ]
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tail call void asm sideeffect "if ($0) vmem($1) = $2;", "q,r,v,~{memory}"(<128 x i1> %v6, <32 x i32>* undef, <32 x i32> undef) #2
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ret void
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}
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declare <128 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32) #1
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declare <128 x i1> @llvm.hexagon.V6.pred.not.128B(<128 x i1>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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