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llvm-mirror/test/CodeGen/Hexagon/inline-asm-a.ll
Krzysztof Parzyszek 98e89321ce [Hexagon] Add inline-asm constraint 'a' for modifier register class
For example
  asm ("memw(%0++%1) = %2" : : "r"(addr),"a"(mod),"r"(val) : "memory")

llvm-svn: 308761
2017-07-21 17:51:27 +00:00

17 lines
425 B
LLVM

; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that constraint a is handled correctly.
; CHECK: [[M:m[01]]] = r1
; CHECK: memw(r0++[[M]]) = r2
target triple = "hexagon"
; Function Attrs: nounwind
define void @foo(i32* %a, i32 %m, i32 %v) #0 {
entry:
tail call void asm sideeffect "memw($0++$1) = $2", "r,a,r,~{memory}"(i32* %a, i32 %m, i32 %v)
ret void
}
attributes #0 = { nounwind "target-cpu"="hexagonv60" }