1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-26 04:32:44 +01:00
llvm-mirror/test/CodeGen/Hexagon/struct_args.ll
Krzysztof Parzyszek 6d72583592 [Hexagon] Bitwise operations for insert/extract word not simplified
Change the bit simplifier to generate REG_SEQUENCE instructions in
addition to COPY, which will handle cases of word insert/extract.

llvm-svn: 276787
2016-07-26 18:30:11 +00:00

17 lines
369 B
LLVM

; RUN: llc -march=hexagon -disable-hsdr < %s | FileCheck %s
; CHECK-DAG: r0 = memw
; CHECK-DAG: r1 = memw
%struct.small = type { i32, i32 }
@s1 = common global %struct.small zeroinitializer, align 4
define void @foo() nounwind {
entry:
%0 = load i64, i64* bitcast (%struct.small* @s1 to i64*), align 4
call void @bar(i64 %0)
ret void
}
declare void @bar(i64)