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25cc728d30
Summary: This extends the PeelingModuloScheduleExpander to generate prolog and epilog code, and correctly stitch uses through the prolog, kernel, epilog DAG. The key concept in this patch is to ensure that all transforms are *local*; only a function of a block and its immediate predecessor and successor. By defining the problem in this way we can inductively rewrite the entire DAG using only local knowledge that is easy to reason about. For example, we assume that all prologs and epilogs are near-perfect clones of the steady-state kernel. This means that if a block has an instruction that is predicated out, we can redirect all users of that instruction to that equivalent instruction in our immediate predecessor. As all blocks are clones, every instruction must have an equivalent in every other block. Similarly we can make the assumption by construction that if a value defined in a block is used outside that block, the only possible user is its immediate successors. We maintain this even for values that are used outside the loop by creating a limited form of LCSSA. This code isn't small, but it isn't complex. Enabled a bunch of testing from Hexagon. There are a couple of tests not enabled yet; I'm about 80% sure there isn't buggy codegen but the tests are checking for patterns that we don't produce. Those still need a bit more investigation. In the meantime we (Google) are happy with the code produced by this on our downstream SMS implementation, and believe it generates correct code. Subscribers: mgorny, hiraditya, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68205 llvm-svn: 373462
131 lines
4.5 KiB
LLVM
131 lines
4.5 KiB
LLVM
; RUN: llc -march=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s
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; CHECK: loop0(.LBB0_{{[0-9]+}},#347)
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target triple = "hexagon"
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; Function Attrs: norecurse nounwind optsize readonly
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define i32 @f0(i32 %a0, i8* nocapture readonly %a1, i32 %a2) local_unnamed_addr #0 {
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b0:
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%v0 = lshr i32 %a0, 16
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%v1 = and i32 %a0, 65535
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%v2 = icmp ugt i32 %a2, 5551
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br i1 %v2, label %b1, label %b4
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b1: ; preds = %b0, %b3
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%v3 = phi i32 [ %v96, %b3 ], [ %v0, %b0 ]
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%v4 = phi i32 [ %v7, %b3 ], [ %a2, %b0 ]
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%v5 = phi i8* [ %v94, %b3 ], [ %a1, %b0 ]
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%v6 = phi i32 [ %v95, %b3 ], [ %v1, %b0 ]
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br label %b2
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b2: ; preds = %b2, %b1
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%v8 = phi i32 [ %v6, %b1 ], [ %v89, %b2 ]
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%v9 = phi i8* [ %v5, %b1 ], [ %v91, %b2 ]
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%v10 = phi i32 [ %v3, %b1 ], [ %v90, %b2 ]
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%v11 = phi i32 [ 347, %b1 ], [ %v92, %b2 ]
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%v12 = load i8, i8* %v9, align 1, !tbaa !0
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%v13 = zext i8 %v12 to i32
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%v14 = add i32 %v8, %v13
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%v15 = add i32 %v14, %v10
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%v16 = getelementptr inbounds i8, i8* %v9, i32 1
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%v17 = load i8, i8* %v16, align 1, !tbaa !0
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%v18 = zext i8 %v17 to i32
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%v19 = add i32 %v14, %v18
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%v20 = add i32 %v15, %v19
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%v21 = getelementptr inbounds i8, i8* %v9, i32 2
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%v22 = load i8, i8* %v21, align 1, !tbaa !0
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%v23 = zext i8 %v22 to i32
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%v24 = add i32 %v19, %v23
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%v25 = add i32 %v20, %v24
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%v26 = getelementptr inbounds i8, i8* %v9, i32 3
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%v27 = load i8, i8* %v26, align 1, !tbaa !0
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%v28 = zext i8 %v27 to i32
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%v29 = add i32 %v24, %v28
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%v30 = add i32 %v25, %v29
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%v31 = getelementptr inbounds i8, i8* %v9, i32 4
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%v32 = load i8, i8* %v31, align 1, !tbaa !0
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%v33 = zext i8 %v32 to i32
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%v34 = add i32 %v29, %v33
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%v35 = add i32 %v30, %v34
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%v36 = getelementptr inbounds i8, i8* %v9, i32 5
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%v37 = load i8, i8* %v36, align 1, !tbaa !0
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%v38 = zext i8 %v37 to i32
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%v39 = add i32 %v34, %v38
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%v40 = add i32 %v35, %v39
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%v41 = getelementptr inbounds i8, i8* %v9, i32 6
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%v42 = load i8, i8* %v41, align 1, !tbaa !0
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%v43 = zext i8 %v42 to i32
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%v44 = add i32 %v39, %v43
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%v45 = add i32 %v40, %v44
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%v46 = getelementptr inbounds i8, i8* %v9, i32 7
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%v47 = load i8, i8* %v46, align 1, !tbaa !0
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%v48 = zext i8 %v47 to i32
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%v49 = add i32 %v44, %v48
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%v50 = add i32 %v45, %v49
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%v51 = getelementptr inbounds i8, i8* %v9, i32 8
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%v52 = load i8, i8* %v51, align 1, !tbaa !0
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%v53 = zext i8 %v52 to i32
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%v54 = add i32 %v49, %v53
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%v55 = add i32 %v50, %v54
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%v56 = getelementptr inbounds i8, i8* %v9, i32 9
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%v57 = load i8, i8* %v56, align 1, !tbaa !0
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%v58 = zext i8 %v57 to i32
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%v59 = add i32 %v54, %v58
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%v60 = add i32 %v55, %v59
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%v61 = getelementptr inbounds i8, i8* %v9, i32 10
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%v62 = load i8, i8* %v61, align 1, !tbaa !0
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%v63 = zext i8 %v62 to i32
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%v64 = add i32 %v59, %v63
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%v65 = add i32 %v60, %v64
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%v66 = getelementptr inbounds i8, i8* %v9, i32 11
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%v67 = load i8, i8* %v66, align 1, !tbaa !0
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%v68 = zext i8 %v67 to i32
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%v69 = add i32 %v64, %v68
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%v70 = add i32 %v65, %v69
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%v71 = getelementptr inbounds i8, i8* %v9, i32 12
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%v72 = load i8, i8* %v71, align 1, !tbaa !0
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%v73 = zext i8 %v72 to i32
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%v74 = add i32 %v69, %v73
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%v75 = add i32 %v70, %v74
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%v76 = getelementptr inbounds i8, i8* %v9, i32 13
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%v77 = load i8, i8* %v76, align 1, !tbaa !0
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%v78 = zext i8 %v77 to i32
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%v79 = add i32 %v74, %v78
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%v80 = add i32 %v75, %v79
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%v81 = getelementptr inbounds i8, i8* %v9, i32 14
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%v82 = load i8, i8* %v81, align 1, !tbaa !0
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%v83 = zext i8 %v82 to i32
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%v84 = add i32 %v79, %v83
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%v85 = add i32 %v80, %v84
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%v86 = getelementptr inbounds i8, i8* %v9, i32 15
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%v87 = load i8, i8* %v86, align 1, !tbaa !0
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%v88 = zext i8 %v87 to i32
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%v89 = add i32 %v84, %v88
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%v90 = add i32 %v85, %v89
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%v91 = getelementptr inbounds i8, i8* %v9, i32 16
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%v92 = add nsw i32 %v11, -1
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%v93 = icmp eq i32 %v92, 0
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br i1 %v93, label %b3, label %b2
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b3: ; preds = %b2
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%v7 = add i32 %v4, -5552
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%v94 = getelementptr i8, i8* %v5, i32 5552
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%v95 = urem i32 %v89, 65521
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%v96 = urem i32 %v90, 65521
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%v97 = icmp ugt i32 %v7, 5551
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br i1 %v97, label %b1, label %b4
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b4: ; preds = %b3, %b0
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%v98 = phi i32 [ %v0, %b0 ], [ %v96, %b3 ]
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%v99 = phi i32 [ %v1, %b0 ], [ %v95, %b3 ]
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%v100 = shl nuw i32 %v98, 16
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%v101 = or i32 %v100, %v99
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ret i32 %v101
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}
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attributes #0 = { norecurse nounwind optsize readonly "target-cpu"="hexagonv55" }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"omnipotent char", !2, i64 0}
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!2 = !{!"Simple C/C++ TBAA"}
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