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https://github.com/RPCS3/llvm-mirror.git
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c28d8cf19b
This commit removes the artificial types <512 x i1> and <1024 x i1>
from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal on
Hexagon.
It may cause existing bitcode files to become invalid.
* Converting between vector predicates and vector registers must be
done explicitly via vandvrt/vandqrt instructions (their intrinsics),
i.e. (for 64-byte mode):
%Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1)
%V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1)
The conversion intrinsics are:
declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32)
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32)
They are all pure.
* Vector predicate values cannot be loaded/stored directly. This directly
reflects the architecture restriction. Loading and storing or vector
predicates must be done indirectly via vector registers and explicit
conversions via vandvrt/vandqrt instructions.
56 lines
2.2 KiB
LLVM
56 lines
2.2 KiB
LLVM
; RUN: llc -march=hexagon -rdf-opt=0 < %s -pipeliner-experimental-cg=true | FileCheck %s
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; Test that we generate the correct name for a value in a prolog block. The
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; pipeliner was using an incorrect value for an instruction in the 2nd prolog
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; block for a value defined by a Phi. The result was that an instruction in
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; the 1st and 2nd prolog blocks contain the same operands.
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; CHECK: vcmp.gt([[VREG:(v[0-9]+)]].uh,v{{[0-9]+}}.uh)
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; CHECK-NOT: vcmp.gt([[VREG]].uh,v{{[0-9]+}}.uh)
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; CHECK: loop0
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define void @f0(<64 x i32> %a0, <32 x i32> %a1, i32 %a2) #0 {
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b0:
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br i1 undef, label %b1, label %b5
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b1: ; preds = %b0
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%v0 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %a0)
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br label %b2
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b2: ; preds = %b4, %b1
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%v1 = phi <32 x i32> [ %a1, %b1 ], [ %v7, %b4 ]
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br label %b3
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b3: ; preds = %b3, %b2
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%v2 = phi i32 [ 0, %b2 ], [ %v8, %b3 ]
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%v3 = phi <32 x i32> [ zeroinitializer, %b2 ], [ %v0, %b3 ]
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%v4 = phi <32 x i32> [ %v1, %b2 ], [ %v7, %b3 ]
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%v5 = tail call <128 x i1> @llvm.hexagon.V6.vgtuh.128B(<32 x i32> %v3, <32 x i32> undef)
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%v6 = tail call <128 x i1> @llvm.hexagon.V6.veqh.and.128B(<128 x i1> %v5, <32 x i32> undef, <32 x i32> undef)
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%v7 = tail call <32 x i32> @llvm.hexagon.V6.vaddhq.128B(<128 x i1> %v6, <32 x i32> %v4, <32 x i32> undef)
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%v8 = add nsw i32 %v2, 1
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%v9 = icmp slt i32 %v8, %a2
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br i1 %v9, label %b3, label %b4
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b4: ; preds = %b3
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br i1 undef, label %b5, label %b2
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b5: ; preds = %b4, %b0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <128 x i1> @llvm.hexagon.V6.vgtuh.128B(<32 x i32>, <32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <128 x i1> @llvm.hexagon.V6.veqh.and.128B(<128 x i1>, <32 x i32>, <32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vaddhq.128B(<128 x i1>, <32 x i32>, <32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
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attributes #1 = { nounwind readnone }
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