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44 lines
1.4 KiB
LLVM
44 lines
1.4 KiB
LLVM
; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
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; CHECK: v{{[0-9]+}} = vsplat(r{{[0-9]+}})
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; CHECK: .comm g0,256,256
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; CHECK: .comm g1,128,128
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target triple = "hexagon"
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@g0 = common global <64 x i32> zeroinitializer, align 256
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@g1 = common global <32 x i32> zeroinitializer, align 128
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; Function Attrs: nounwind
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define i32 @f0() #0 {
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b0:
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%v0 = alloca i32, align 4
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store i32 0, i32* %v0
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%v1 = call i32 @f1(i8 zeroext 0)
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call void bitcast (void (...)* @f2 to void ()*)()
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%v2 = call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 1)
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%v3 = call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 2)
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%v4 = call <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32> %v2, <32 x i32> %v3)
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%v5 = call <64 x i32> @llvm.hexagon.V6.vtmpyhb.128B(<64 x i32> %v4, i32 12)
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store <64 x i32> %v5, <64 x i32>* @g0, align 256
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call void @f3(i32 2048, i8* bitcast (<64 x i32>* @g0 to i8*))
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ret i32 0
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}
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declare i32 @f1(i8 zeroext) #0
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declare void @f2(...) #0
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; Function Attrs: nounwind readnone
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declare <64 x i32> @llvm.hexagon.V6.vtmpyhb.128B(<64 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <64 x i32> @llvm.hexagon.V6.vaddubh.128B(<32 x i32>, <32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32) #1
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declare void @f3(i32, i8*) #0
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
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attributes #1 = { nounwind readnone }
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