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https://github.com/RPCS3/llvm-mirror.git
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c28d8cf19b
This commit removes the artificial types <512 x i1> and <1024 x i1>
from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal on
Hexagon.
It may cause existing bitcode files to become invalid.
* Converting between vector predicates and vector registers must be
done explicitly via vandvrt/vandqrt instructions (their intrinsics),
i.e. (for 64-byte mode):
%Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1)
%V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1)
The conversion intrinsics are:
declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32)
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32)
They are all pure.
* Vector predicate values cannot be loaded/stored directly. This directly
reflects the architecture restriction. Loading and storing or vector
predicates must be done indirectly via vector registers and explicit
conversions via vandvrt/vandqrt instructions.
108 lines
4.0 KiB
LLVM
108 lines
4.0 KiB
LLVM
; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
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; Looking for 3rd register field to be restricted to r0-r7.
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; v3:2=vdeal(v3,v2,r1)
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; CHECK: v{{[0-9]+}}:{{[0-9]+}} = vdeal(v{{[0-9]+}},v{{[0-9]+}},r{{[0-7]+}})
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @f0(i16* %a0, i32 %a1, i8* %a2, i16* %a3) #0 {
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b0:
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%v0 = alloca i16*, align 4
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%v1 = alloca i32, align 4
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%v2 = alloca i8*, align 4
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%v3 = alloca i16*, align 4
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%v4 = alloca i32, align 4
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%v5 = alloca i32, align 4
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%v6 = alloca i32, align 4
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%v7 = alloca i32, align 4
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%v8 = alloca i32, align 4
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%v9 = alloca i16*, align 4
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%v10 = alloca i16*, align 4
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%v11 = alloca <16 x i32>, align 64
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%v12 = alloca <16 x i32>, align 64
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%v13 = alloca <32 x i32>, align 128
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%v14 = alloca <16 x i32>, align 64
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%v15 = alloca <16 x i32>, align 64
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%v16 = alloca <32 x i32>, align 128
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%v17 = alloca <16 x i32>, align 64
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%v18 = alloca <16 x i32>, align 64
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store i16* %a0, i16** %v0, align 4
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store i32 %a1, i32* %v1, align 4
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store i8* %a2, i8** %v2, align 4
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store i16* %a3, i16** %v3, align 4
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%v19 = load i8*, i8** %v2, align 4
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%v20 = getelementptr inbounds i8, i8* %v19, i32 192
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%v21 = bitcast i8* %v20 to <16 x i32>*
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%v22 = load <16 x i32>, <16 x i32>* %v21, align 64
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store <16 x i32> %v22, <16 x i32>* %v12, align 64
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store i32 16843009, i32* %v4, align 4
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%v23 = load i32, i32* %v4, align 4
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%v24 = load i32, i32* %v4, align 4
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%v25 = add nsw i32 %v23, %v24
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store i32 %v25, i32* %v5, align 4
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%v26 = load i32, i32* %v5, align 4
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%v27 = load i32, i32* %v5, align 4
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%v28 = add nsw i32 %v26, %v27
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store i32 %v28, i32* %v6, align 4
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%v29 = load i16*, i16** %v0, align 4
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store i16* %v29, i16** %v9, align 4
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%v30 = load i16*, i16** %v3, align 4
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store i16* %v30, i16** %v10, align 4
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store i32 0, i32* %v8, align 4
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br label %b1
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b1: ; preds = %b3, %b0
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%v31 = load i32, i32* %v8, align 4
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%v32 = load i32, i32* %v1, align 4
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%v33 = icmp slt i32 %v31, %v32
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br i1 %v33, label %b2, label %b4
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b2: ; preds = %b1
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%v34 = load <16 x i32>, <16 x i32>* %v11, align 64
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%v35 = tail call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %v34, i32 -1)
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%v36 = load <16 x i32>, <16 x i32>* %v14, align 64
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%v37 = load <16 x i32>, <16 x i32>* %v15, align 64
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%v38 = call <32 x i32> @llvm.hexagon.V6.vswap(<64 x i1> %v35, <16 x i32> %v36, <16 x i32> %v37)
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store <32 x i32> %v38, <32 x i32>* %v13, align 128
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%v39 = load <32 x i32>, <32 x i32>* %v13, align 128
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%v40 = call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %v39)
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store <16 x i32> %v40, <16 x i32>* %v14, align 64
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%v41 = load <32 x i32>, <32 x i32>* %v13, align 128
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%v42 = call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %v41)
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store <16 x i32> %v42, <16 x i32>* %v15, align 64
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%v43 = load <16 x i32>, <16 x i32>* %v17, align 64
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%v44 = load <16 x i32>, <16 x i32>* %v18, align 64
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%v45 = load i32, i32* %v7, align 4
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%v46 = call <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32> %v43, <16 x i32> %v44, i32 %v45)
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store <32 x i32> %v46, <32 x i32>* %v16, align 128
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br label %b3
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b3: ; preds = %b2
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%v47 = load i32, i32* %v8, align 4
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%v48 = add nsw i32 %v47, 1
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store i32 %v48, i32* %v8, align 4
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br label %b1
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b4: ; preds = %b1
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vswap(<64 x i1>, <16 x i32>, <16 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vdealvdd(<16 x i32>, <16 x i32>, i32) #1
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; Function Attrs: nounwind readnone
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declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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