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c28d8cf19b
This commit removes the artificial types <512 x i1> and <1024 x i1>
from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal on
Hexagon.
It may cause existing bitcode files to become invalid.
* Converting between vector predicates and vector registers must be
done explicitly via vandvrt/vandqrt instructions (their intrinsics),
i.e. (for 64-byte mode):
%Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1)
%V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1)
The conversion intrinsics are:
declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32)
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32)
They are all pure.
* Vector predicate values cannot be loaded/stored directly. This directly
reflects the architecture restriction. Loading and storing or vector
predicates must be done indirectly via vector registers and explicit
conversions via vandvrt/vandqrt instructions.
34 lines
1.3 KiB
LLVM
34 lines
1.3 KiB
LLVM
; RUN: llc -march=hexagon -mattr="+hvxv60,+hvx-length64b" < %s
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; REQUIRES: asserts
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target triple = "hexagon"
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; Function Attrs: nounwind
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define void @fred() #0 {
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entry:
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br label %for.body9.us
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for.body9.us:
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%cmp10.us = icmp eq i32 0, undef
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%.h63h32.2.us = select i1 %cmp10.us, <16 x i32> zeroinitializer, <16 x i32> undef
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%0 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %.h63h32.2.us, <16 x i32> undef, i32 2)
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%1 = tail call <32 x i32> @llvm.hexagon.V6.vswap(<64 x i1> undef, <16 x i32> undef, <16 x i32> %0)
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%2 = tail call <16 x i32> @llvm.hexagon.V6.lo(<32 x i32> %1)
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%3 = tail call <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32> undef, <16 x i32> %2, i32 62)
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%4 = tail call <16 x i32> @llvm.hexagon.V6.hi(<32 x i32> %3)
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store <16 x i32> %4, <16 x i32>* undef, align 64
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br i1 undef, label %for.body9.us, label %for.body43.us.preheader
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for.body43.us.preheader: ; preds = %for.body9.us
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ret void
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}
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declare <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32>, <16 x i32>, i32) #1
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declare <32 x i32> @llvm.hexagon.V6.vswap(<64 x i1>, <16 x i32>, <16 x i32>) #1
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declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1
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declare <16 x i32> @llvm.hexagon.V6.lo(<32 x i32>) #1
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declare <32 x i32> @llvm.hexagon.V6.vshuffvdd(<16 x i32>, <16 x i32>, i32) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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