mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-22 18:54:02 +01:00
cc12b285b6
This will currently accept the old number of bytes syntax, and convert it to a scalar. This should be removed in the near future (I think I converted all of the tests already, but likely missed a few). Not sure what the exact syntax and policy should be. We can continue printing the number of bytes for non-generic instructions to avoid test churn and only allow non-scalar types for generic instructions. This will currently print the LLT in parentheses, but accept parsing the existing integers and implicitly converting to scalar. The parentheses are a bit ugly, but the parser logic seems unable to deal without either parentheses or some keyword to indicate the start of a type.
77 lines
3.4 KiB
YAML
77 lines
3.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv7m-none-eabi -run-pass=arm-cp-islands -verify-machineinstrs -o - %s | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.1m.main-arm-none-eabi"
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@a = global i32 0, align 4
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@b = local_unnamed_addr global i32 0, align 4
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define i32 @c() {
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entry:
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br i1 icmp eq (i8 trunc (i32 sdiv (i32 zext (i8 trunc (i32 lshr (i32 zext (i8 ptrtoint (i32* @a to i8) to i32), i32 6) to i8) to i32), i32 7) to i8), i8 0), label %if.then, label %safe_mod_func_int32_t_s_s.exit
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safe_mod_func_int32_t_s_s.exit: ; preds = %entry
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br i1 icmp eq (i32 srem (i32 6, i32 zext (i8 trunc (i32 sdiv (i32 zext (i8 trunc (i32 lshr (i32 zext (i8 ptrtoint (i32* @a to i8) to i32), i32 6) to i8) to i32), i32 7) to i8) to i32)), i32 0), label %if.end, label %if.then
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if.then: ; preds = %safe_mod_func_int32_t_s_s.exit, %entry
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%0 = load i32, i32* @b, align 4
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%inc = add nsw i32 %0, 1
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store i32 %inc, i32* @b, align 4
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br label %if.end
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if.end: ; preds = %if.then, %safe_mod_func_int32_t_s_s.exit
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ret i32 undef
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}
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...
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---
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name: c
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alignment: 2
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: c
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.2(0x40000000), %bb.1(0x40000000)
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; CHECK: renamable $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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; CHECK: tCBNZ killed renamable $r0, %bb.2
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; CHECK: bb.1.safe_mod_func_int32_t_s_s.exit:
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; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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; CHECK: tCBZ undef renamable $r0, %bb.3
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; CHECK: bb.2.if.then:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: $r0 = t2MOVi16 target-flags(arm-lo16) @b, 14 /* CC::al */, $noreg
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; CHECK: $r0 = t2MOVTi16 killed $r0, target-flags(arm-hi16) @b, 14 /* CC::al */, $noreg
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; CHECK: renamable $r1 = tLDRi renamable $r0, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from @b)
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; CHECK: renamable $r1, dead $cpsr = nsw tADDi8 killed renamable $r1, 1, 14 /* CC::al */, $noreg
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; CHECK: tSTRi killed renamable $r1, killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (store (s32) into @b)
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; CHECK: bb.3.if.end:
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; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit undef $r0
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bb.0.entry:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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renamable $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
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tCMPi8 killed renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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t2Bcc %bb.2, 1 /* CC::ne */, killed $cpsr
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bb.1.safe_mod_func_int32_t_s_s.exit:
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successors: %bb.3(0x40000000), %bb.2(0x40000000)
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tCMPi8 undef renamable $r0, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
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t2Bcc %bb.3, 0 /* CC::eq */, killed $cpsr
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bb.2.if.then:
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successors: %bb.3(0x80000000)
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$r0 = t2MOVi16 target-flags(arm-lo16) @b, 14 /* CC::al */, $noreg
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$r0 = t2MOVTi16 killed $r0, target-flags(arm-hi16) @b, 14 /* CC::al */, $noreg
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renamable $r1 = tLDRi renamable $r0, 0, 14 /* CC::al */, $noreg :: (dereferenceable load (s32) from @b)
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renamable $r1, dead $cpsr = nsw tADDi8 killed renamable $r1, 1, 14 /* CC::al */, $noreg
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tSTRi killed renamable $r1, killed renamable $r0, 0, 14 /* CC::al */, $noreg :: (store (s32) into @b)
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bb.3.if.end:
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tBX_RET 14 /* CC::al */, $noreg, implicit undef $r0
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...
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