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llvm-mirror/test/CodeGen/Thumb2/constant-islands-ldrsb.mir
Matt Arsenault cc12b285b6 CodeGen: Print/parse LLTs in MachineMemOperands
This will currently accept the old number of bytes syntax, and convert
it to a scalar. This should be removed in the near future (I think I
converted all of the tests already, but likely missed a few).

Not sure what the exact syntax and policy should be. We can continue
printing the number of bytes for non-generic instructions to avoid
test churn and only allow non-scalar types for generic instructions.

This will currently print the LLT in parentheses, but accept parsing
the existing integers and implicitly converting to scalar. The
parentheses are a bit ugly, but the parser logic seems unable to deal
without either parentheses or some keyword to indicate the start of a
type.
2021-06-30 16:54:13 -04:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main-none-eabi -run-pass=arm-cp-islands -o - %s | FileCheck %s
# CHECK-NOT: Unknown addressing mode for CP reference
--- |
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv8.1m.main-arm-none-eabi"
define void @t2LDRSBpci() { ret void }
define void @t2LDRSHpci() { ret void }
...
---
name: t2LDRSBpci
alignment: 4
tracksRegLiveness: true
constants:
- id: 0
value: 'i32 0'
alignment: 4
body: |
bb.0:
$sp = frame-setup tSUBspi $sp, 3, 14 /* CC::al */, $noreg
frame-setup CFI_INSTRUCTION def_cfa_offset 12
renamable $r0 = t2LDRSBpci %const.0, 14 /* CC::al */, $noreg :: (dereferenceable load (s8), align 4)
renamable $r1 = tMOVr $sp, 14 /* CC::al */, $noreg
tCMPr killed renamable $r1, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
$r1 = t2MOVi16 target-flags(arm-lo16) @t2LDRSBpci, 14 /* CC::al */, $noreg
renamable $r0 = t2CSINC $zr, $zr, 3, implicit killed $cpsr
$r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @t2LDRSBpci, 14 /* CC::al */, $noreg
tSTRi killed renamable $r0, killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (store (s32))
$sp = frame-destroy tADDspi $sp, 3, 14 /* CC::al */, $noreg
tBX_RET 14 /* CC::al */, $noreg
...
---
name: t2LDRSHpci
alignment: 4
tracksRegLiveness: true
constants:
- id: 0
value: 'i32 0'
alignment: 4
body: |
bb.0:
$sp = frame-setup tSUBspi $sp, 3, 14 /* CC::al */, $noreg
frame-setup CFI_INSTRUCTION def_cfa_offset 12
renamable $r0 = t2LDRSHpci %const.0, 14 /* CC::al */, $noreg :: (dereferenceable load (s8), align 4)
renamable $r1 = tMOVr $sp, 14 /* CC::al */, $noreg
tCMPr killed renamable $r1, killed renamable $r0, 14 /* CC::al */, $noreg, implicit-def $cpsr
$r1 = t2MOVi16 target-flags(arm-lo16) @t2LDRSHpci, 14 /* CC::al */, $noreg
renamable $r0 = t2CSINC $zr, $zr, 3, implicit killed $cpsr
$r1 = t2MOVTi16 killed $r1, target-flags(arm-hi16) @t2LDRSHpci, 14 /* CC::al */, $noreg
tSTRi killed renamable $r0, killed renamable $r1, 0, 14 /* CC::al */, $noreg :: (store (s32))
$sp = frame-destroy tADDspi $sp, 3, 14 /* CC::al */, $noreg
tBX_RET 14 /* CC::al */, $noreg
...