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ae50d26182
Propagate undef through VECTOR_REG_CAST nodes, allowing extra simplification in some patterns.
368 lines
12 KiB
LLVM
368 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
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; RUN: llc -mtriple=thumbebv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
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define void @load_load_add_store(<4 x i32> *%src1, <4 x i32> *%src2) {
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; CHECK-LABEL: load_load_add_store:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q0, [r1]
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; CHECK-NEXT: vldrw.u32 q1, [r0]
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; CHECK-NEXT: vadd.i32 q0, q1, q0
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; CHECK-NEXT: vstrw.32 q0, [r0]
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; CHECK-NEXT: bx lr
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entry:
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%l1 = load <4 x i32>, <4 x i32>* %src1, align 4
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%l2 = load <4 x i32>, <4 x i32>* %src2, align 4
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%a = add <4 x i32> %l1, %l2
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store <4 x i32> %a, <4 x i32>* %src1, align 4
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ret void
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}
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define void @load_load_add_store_align1(<4 x i32> *%src1, <4 x i32> *%src2) {
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; CHECK-LE-LABEL: load_load_add_store_align1:
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; CHECK-LE: @ %bb.0: @ %entry
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; CHECK-LE-NEXT: vldrb.u8 q0, [r1]
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; CHECK-LE-NEXT: vldrb.u8 q1, [r0]
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; CHECK-LE-NEXT: vadd.i32 q0, q1, q0
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; CHECK-LE-NEXT: vstrb.8 q0, [r0]
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: load_load_add_store_align1:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: vldrb.u8 q0, [r1]
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; CHECK-BE-NEXT: vldrb.u8 q1, [r0]
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; CHECK-BE-NEXT: vrev32.8 q0, q0
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; CHECK-BE-NEXT: vrev32.8 q1, q1
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; CHECK-BE-NEXT: vadd.i32 q0, q1, q0
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; CHECK-BE-NEXT: vrev32.8 q0, q0
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; CHECK-BE-NEXT: vstrb.8 q0, [r0]
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; CHECK-BE-NEXT: bx lr
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entry:
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%l1 = load <4 x i32>, <4 x i32>* %src1, align 1
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%l2 = load <4 x i32>, <4 x i32>* %src2, align 1
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%a = add <4 x i32> %l1, %l2
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store <4 x i32> %a, <4 x i32>* %src1, align 1
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ret void
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}
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define arm_aapcs_vfpcc void @load_arg_add_store(<4 x i32> *%src1, <4 x i32> %src2) {
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; CHECK-LE-LABEL: load_arg_add_store:
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; CHECK-LE: @ %bb.0: @ %entry
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; CHECK-LE-NEXT: vldrw.u32 q1, [r0]
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; CHECK-LE-NEXT: vadd.i32 q0, q1, q0
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; CHECK-LE-NEXT: vstrw.32 q0, [r0]
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: load_arg_add_store:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: vrev64.32 q1, q0
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; CHECK-BE-NEXT: vldrw.u32 q0, [r0]
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; CHECK-BE-NEXT: vadd.i32 q0, q0, q1
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; CHECK-BE-NEXT: vstrw.32 q0, [r0]
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; CHECK-BE-NEXT: bx lr
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entry:
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%l1 = load <4 x i32>, <4 x i32>* %src1, align 4
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%a = add <4 x i32> %l1, %src2
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store <4 x i32> %a, <4 x i32>* %src1, align 4
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ret void
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}
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define <4 x i32> @add_soft(<4 x i32> %src1, <4 x i32> %src2) {
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; CHECK-LE-LABEL: add_soft:
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; CHECK-LE: @ %bb.0: @ %entry
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; CHECK-LE-NEXT: vmov d1, r2, r3
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; CHECK-LE-NEXT: vmov d0, r0, r1
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; CHECK-LE-NEXT: mov r0, sp
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; CHECK-LE-NEXT: vldrw.u32 q1, [r0]
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; CHECK-LE-NEXT: vadd.i32 q0, q0, q1
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; CHECK-LE-NEXT: vmov r0, r1, d0
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; CHECK-LE-NEXT: vmov r2, r3, d1
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: add_soft:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: vmov d1, r3, r2
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; CHECK-BE-NEXT: vmov d0, r1, r0
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; CHECK-BE-NEXT: mov r0, sp
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; CHECK-BE-NEXT: vrev64.32 q1, q0
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; CHECK-BE-NEXT: vldrw.u32 q0, [r0]
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; CHECK-BE-NEXT: vadd.i32 q0, q1, q0
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; CHECK-BE-NEXT: vrev64.32 q1, q0
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; CHECK-BE-NEXT: vmov r1, r0, d2
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; CHECK-BE-NEXT: vmov r3, r2, d3
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; CHECK-BE-NEXT: bx lr
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entry:
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%0 = add <4 x i32> %src1, %src2
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @add_hard(<4 x i32> %src1, <4 x i32> %src2) {
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; CHECK-LE-LABEL: add_hard:
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; CHECK-LE: @ %bb.0: @ %entry
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; CHECK-LE-NEXT: vadd.i32 q0, q0, q1
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: add_hard:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: vrev64.32 q2, q1
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; CHECK-BE-NEXT: vrev64.32 q1, q0
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; CHECK-BE-NEXT: vadd.i32 q1, q1, q2
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; CHECK-BE-NEXT: vrev64.32 q0, q1
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; CHECK-BE-NEXT: bx lr
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entry:
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%0 = add <4 x i32> %src1, %src2
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ret <4 x i32> %0
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}
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define <4 x i32> @call_soft(<4 x i32> %src1, <4 x i32> %src2) {
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; CHECK-LE-LABEL: call_soft:
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; CHECK-LE: @ %bb.0: @ %entry
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; CHECK-LE-NEXT: .save {r7, lr}
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; CHECK-LE-NEXT: push {r7, lr}
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; CHECK-LE-NEXT: .pad #16
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; CHECK-LE-NEXT: sub sp, #16
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; CHECK-LE-NEXT: add.w r12, sp, #24
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; CHECK-LE-NEXT: vldrw.u32 q0, [r12]
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; CHECK-LE-NEXT: vstrw.32 q0, [sp]
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; CHECK-LE-NEXT: vmov d1, r2, r3
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; CHECK-LE-NEXT: vmov d0, r0, r1
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; CHECK-LE-NEXT: vshr.u32 q0, q0, #1
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; CHECK-LE-NEXT: vmov r0, r1, d0
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; CHECK-LE-NEXT: vmov r2, r3, d1
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; CHECK-LE-NEXT: bl add_soft
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; CHECK-LE-NEXT: vmov d1, r2, r3
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; CHECK-LE-NEXT: vmov d0, r0, r1
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; CHECK-LE-NEXT: vshr.u32 q0, q0, #1
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; CHECK-LE-NEXT: vmov r0, r1, d0
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; CHECK-LE-NEXT: vmov r2, r3, d1
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; CHECK-LE-NEXT: add sp, #16
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; CHECK-LE-NEXT: pop {r7, pc}
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;
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; CHECK-BE-LABEL: call_soft:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: .save {r7, lr}
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; CHECK-BE-NEXT: push {r7, lr}
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; CHECK-BE-NEXT: .pad #16
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; CHECK-BE-NEXT: sub sp, #16
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; CHECK-BE-NEXT: add.w r12, sp, #24
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; CHECK-BE-NEXT: vldrw.u32 q0, [r12]
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; CHECK-BE-NEXT: vstrw.32 q0, [sp]
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; CHECK-BE-NEXT: vmov d1, r3, r2
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; CHECK-BE-NEXT: vmov d0, r1, r0
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; CHECK-BE-NEXT: vrev64.32 q1, q0
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; CHECK-BE-NEXT: vshr.u32 q0, q1, #1
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; CHECK-BE-NEXT: vrev64.32 q1, q0
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; CHECK-BE-NEXT: vmov r1, r0, d2
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; CHECK-BE-NEXT: vmov r3, r2, d3
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; CHECK-BE-NEXT: bl add_soft
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; CHECK-BE-NEXT: vmov d1, r3, r2
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; CHECK-BE-NEXT: vmov d0, r1, r0
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; CHECK-BE-NEXT: vrev64.32 q1, q0
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; CHECK-BE-NEXT: vshr.u32 q0, q1, #1
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; CHECK-BE-NEXT: vrev64.32 q1, q0
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; CHECK-BE-NEXT: vmov r1, r0, d2
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; CHECK-BE-NEXT: vmov r3, r2, d3
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; CHECK-BE-NEXT: add sp, #16
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; CHECK-BE-NEXT: pop {r7, pc}
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entry:
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%0 = lshr <4 x i32> %src1, <i32 1, i32 1, i32 1, i32 1>
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%1 = call <4 x i32> @add_soft(<4 x i32> %0, <4 x i32> %src2)
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%2 = lshr <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %2
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}
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define arm_aapcs_vfpcc <4 x i32> @call_hard(<4 x i32> %src1, <4 x i32> %src2) {
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; CHECK-LE-LABEL: call_hard:
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; CHECK-LE: @ %bb.0: @ %entry
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; CHECK-LE-NEXT: .save {r7, lr}
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; CHECK-LE-NEXT: push {r7, lr}
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; CHECK-LE-NEXT: vshr.u32 q0, q0, #1
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; CHECK-LE-NEXT: bl add_hard
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; CHECK-LE-NEXT: vshr.u32 q0, q0, #1
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; CHECK-LE-NEXT: pop {r7, pc}
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;
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; CHECK-BE-LABEL: call_hard:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: .save {r7, lr}
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; CHECK-BE-NEXT: push {r7, lr}
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; CHECK-BE-NEXT: vrev64.32 q2, q0
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; CHECK-BE-NEXT: vshr.u32 q2, q2, #1
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; CHECK-BE-NEXT: vrev64.32 q0, q2
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; CHECK-BE-NEXT: bl add_hard
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; CHECK-BE-NEXT: vrev64.32 q1, q0
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; CHECK-BE-NEXT: vshr.u32 q1, q1, #1
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; CHECK-BE-NEXT: vrev64.32 q0, q1
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; CHECK-BE-NEXT: pop {r7, pc}
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entry:
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%0 = lshr <4 x i32> %src1, <i32 1, i32 1, i32 1, i32 1>
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%1 = call arm_aapcs_vfpcc <4 x i32> @add_hard(<4 x i32> %0, <4 x i32> %src2)
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%2 = lshr <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
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ret <4 x i32> %2
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}
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define arm_aapcs_vfpcc <16 x i8> @and_v4i32(<4 x i32> %src) {
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; CHECK-LE-LABEL: and_v4i32:
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; CHECK-LE: @ %bb.0: @ %entry
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; CHECK-LE-NEXT: vmov.i32 q1, #0x1
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; CHECK-LE-NEXT: vand q0, q0, q1
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: and_v4i32:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: vrev64.32 q1, q0
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; CHECK-BE-NEXT: vmov.i32 q0, #0x1
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; CHECK-BE-NEXT: vand q1, q1, q0
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; CHECK-BE-NEXT: vrev64.32 q0, q1
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; CHECK-BE-NEXT: bx lr
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entry:
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%s1 = and <4 x i32> %src, <i32 1, i32 1, i32 1, i32 1>
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%r = bitcast <4 x i32> %s1 to <16 x i8>
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ret <16 x i8> %r
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}
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; Should be the same as and_v4i32 for LE
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define arm_aapcs_vfpcc <16 x i8> @and_v16i8_le(<4 x i32> %src) {
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; CHECK-LE-LABEL: and_v16i8_le:
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; CHECK-LE: @ %bb.0: @ %entry
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; CHECK-LE-NEXT: vmov.i32 q1, #0x1
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; CHECK-LE-NEXT: vand q0, q0, q1
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: and_v16i8_le:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: vrev64.8 q1, q0
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; CHECK-BE-NEXT: vmov.i32 q0, #0x1
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; CHECK-BE-NEXT: vrev32.8 q0, q0
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; CHECK-BE-NEXT: vand q1, q1, q0
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; CHECK-BE-NEXT: vrev64.8 q0, q1
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; CHECK-BE-NEXT: bx lr
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entry:
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%0 = bitcast <4 x i32> %src to <16 x i8>
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%r = and <16 x i8> %0, <i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0>
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ret <16 x i8> %r
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}
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; Should be the same (or at least equivalent) as and_v4i32 for BE
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define arm_aapcs_vfpcc <16 x i8> @and_v16i8_be(<4 x i32> %src) {
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; CHECK-LE-LABEL: and_v16i8_be:
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; CHECK-LE: @ %bb.0: @ %entry
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; CHECK-LE-NEXT: vmov.i32 q1, #0x1000000
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; CHECK-LE-NEXT: vand q0, q0, q1
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: and_v16i8_be:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: vrev64.8 q1, q0
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; CHECK-BE-NEXT: vmov.i32 q0, #0x1000000
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; CHECK-BE-NEXT: vrev32.8 q0, q0
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; CHECK-BE-NEXT: vand q1, q1, q0
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; CHECK-BE-NEXT: vrev64.8 q0, q1
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; CHECK-BE-NEXT: bx lr
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entry:
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%0 = bitcast <4 x i32> %src to <16 x i8>
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%r = and <16 x i8> %0, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
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ret <16 x i8> %r
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}
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; FIXME: This looks wrong
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define arm_aapcs_vfpcc <4 x i32> @test(i32* %data) {
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; CHECK-LE-LABEL: test:
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; CHECK-LE: @ %bb.0: @ %entry
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; CHECK-LE-NEXT: vldrw.u32 q1, [r0, #32]
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; CHECK-LE-NEXT: vmov.i32 q0, #0x1
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; CHECK-LE-NEXT: vadd.i32 q1, q1, q0
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; CHECK-LE-NEXT: @APP
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; CHECK-LE-NEXT: vmullb.s32 q0, q1, q1
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; CHECK-LE-NEXT: @NO_APP
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: vldrw.u32 q1, [r0, #32]
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; CHECK-BE-NEXT: vmov.i32 q0, #0x1
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; CHECK-BE-NEXT: vadd.i32 q0, q1, q0
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; CHECK-BE-NEXT: vrev32.8 q0, q0
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; CHECK-BE-NEXT: @APP
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; CHECK-BE-NEXT: vmullb.s32 q1, q0, q0
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; CHECK-BE-NEXT: @NO_APP
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; CHECK-BE-NEXT: vrev64.8 q0, q1
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; CHECK-BE-NEXT: bx lr
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entry:
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%add.ptr = getelementptr inbounds i32, i32* %data, i32 8
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%0 = bitcast i32* %add.ptr to <4 x i32>*
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%1 = load <4 x i32>, <4 x i32>* %0, align 4
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%2 = add <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
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%3 = tail call <4 x i32> asm sideeffect " VMULLB.s32 $0, $1, $1", "=&w,w"(<4 x i32> %2) #2
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ret <4 x i32> %3
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}
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; Test case demonstrating that 'bitcast' reinterprets the memory format of a
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; vector, as if stored and then loaded. So if it has to go between two
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; operations treating a register as having different lane sizes, then in
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; big-endian mode, it has to emit a vrev32.16, which is equivalent to the
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; effect that vstrw.32 followed by vldrh.16 would have.
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define arm_aapcs_vfpcc void @test_bitcast(<4 x i32>* readonly %in, <8 x i16>* %out) {
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; CHECK-LE-LABEL: test_bitcast:
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; CHECK-LE: @ %bb.0: @ %entry
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; CHECK-LE-NEXT: vldrw.u32 q0, [r0]
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; CHECK-LE-NEXT: vmul.i32 q0, q0, q0
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; CHECK-LE-NEXT: vmul.i16 q0, q0, q0
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; CHECK-LE-NEXT: vstrw.32 q0, [r1]
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_bitcast:
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; CHECK-BE: @ %bb.0: @ %entry
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; CHECK-BE-NEXT: vldrw.u32 q0, [r0]
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; CHECK-BE-NEXT: vmul.i32 q0, q0, q0
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; CHECK-BE-NEXT: vrev32.16 q0, q0
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; CHECK-BE-NEXT: vmul.i16 q0, q0, q0
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; CHECK-BE-NEXT: vstrh.16 q0, [r1]
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; CHECK-BE-NEXT: bx lr
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entry:
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%vin = load <4 x i32>, <4 x i32>* %in, align 8
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%vdbl = mul <4 x i32> %vin, %vin
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%cast = bitcast <4 x i32> %vdbl to <8 x i16>
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%cdbl = mul <8 x i16> %cast, %cast
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store <8 x i16> %cdbl, <8 x i16>* %out, align 8
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ret void
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}
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; Similar test case but using the arm.mve.vreinterpretq intrinsic instead,
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; which is defined to reinterpret the in-register format, so it generates no
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; instruction in either endianness.
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define arm_aapcs_vfpcc void @test_vreinterpretq(<4 x i32>* readonly %in, <8 x i16>* %out) {
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; CHECK-LE-LABEL: test_vreinterpretq:
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; CHECK-LE: @ %bb.0: @ %entry
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; CHECK-LE-NEXT: vldrw.u32 q0, [r0]
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; CHECK-LE-NEXT: vmul.i32 q0, q0, q0
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; CHECK-LE-NEXT: vmul.i16 q0, q0, q0
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; CHECK-LE-NEXT: vstrw.32 q0, [r1]
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; CHECK-LE-NEXT: bx lr
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;
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; CHECK-BE-LABEL: test_vreinterpretq:
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; CHECK-BE: @ %bb.0: @ %entry
|
|
; CHECK-BE-NEXT: vldrw.u32 q0, [r0]
|
|
; CHECK-BE-NEXT: vmul.i32 q0, q0, q0
|
|
; CHECK-BE-NEXT: vmul.i16 q0, q0, q0
|
|
; CHECK-BE-NEXT: vstrh.16 q0, [r1]
|
|
; CHECK-BE-NEXT: bx lr
|
|
entry:
|
|
%vin = load <4 x i32>, <4 x i32>* %in, align 8
|
|
%vdbl = mul <4 x i32> %vin, %vin
|
|
%cast = call <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v4i32(<4 x i32> %vdbl)
|
|
%cdbl = mul <8 x i16> %cast, %cast
|
|
store <8 x i16> %cdbl, <8 x i16>* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
define arm_aapcs_vfpcc <8 x half> @undef_one() {
|
|
; CHECK-LABEL: undef_one:
|
|
; CHECK: @ %bb.0:
|
|
; CHECK-NEXT: bx lr
|
|
%c = call <8 x half> @llvm.arm.mve.vreinterpretq.v8f16.v4f32(<4 x float> undef)
|
|
ret <8 x half> %c
|
|
}
|
|
|
|
declare <8 x half> @llvm.arm.mve.vreinterpretq.v8f16.v4f32(<4 x float>)
|
|
declare <8 x i16> @llvm.arm.mve.vreinterpretq.v8i16.v4i32(<4 x i32>)
|