mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-22 18:54:02 +01:00
17e932c916
This adds a combine for extract(x, n); extract(x, n+1) -> VMOVRRD(extract x, n/2). This allows two vector lanes to be moved at the same time in a single instruction, and thanks to the other VMOVRRD folds we have added recently can help reduce the amount of executed instructions. Floating point types are very similar, but will include a bitcast to an integer type. This also adds a shouldRewriteCopySrc, to prevent copy propagation from DPR to SPR, which can break as not all DPR regs can be extracted from directly. Otherwise the machine verifier is unhappy. Differential Revision: https://reviews.llvm.org/D100244
137 lines
3.9 KiB
LLVM
137 lines
3.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s
|
|
|
|
define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_0_t(<2 x i64> %src){
|
|
; CHECK-LABEL: ctlz_2i64_0_t:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vmov r0, r1, d1
|
|
; CHECK-NEXT: clz r0, r0
|
|
; CHECK-NEXT: cmp r1, #0
|
|
; CHECK-NEXT: cset r2, ne
|
|
; CHECK-NEXT: adds r0, #32
|
|
; CHECK-NEXT: cmp r2, #0
|
|
; CHECK-NEXT: it ne
|
|
; CHECK-NEXT: clzne r0, r1
|
|
; CHECK-NEXT: vmov s6, r0
|
|
; CHECK-NEXT: vmov r0, r1, d0
|
|
; CHECK-NEXT: clz r0, r0
|
|
; CHECK-NEXT: cmp r1, #0
|
|
; CHECK-NEXT: cset r2, ne
|
|
; CHECK-NEXT: adds r0, #32
|
|
; CHECK-NEXT: cmp r2, #0
|
|
; CHECK-NEXT: it ne
|
|
; CHECK-NEXT: clzne r0, r1
|
|
; CHECK-NEXT: vmov s4, r0
|
|
; CHECK-NEXT: vldr s5, .LCPI0_0
|
|
; CHECK-NEXT: vmov.f32 s7, s5
|
|
; CHECK-NEXT: vmov q0, q1
|
|
; CHECK-NEXT: bx lr
|
|
; CHECK-NEXT: .p2align 2
|
|
; CHECK-NEXT: @ %bb.1:
|
|
; CHECK-NEXT: .LCPI0_0:
|
|
; CHECK-NEXT: .long 0x00000000 @ float 0
|
|
entry:
|
|
%0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 0)
|
|
ret <2 x i64> %0
|
|
}
|
|
|
|
define arm_aapcs_vfpcc <4 x i32> @ctlz_4i32_0_t(<4 x i32> %src){
|
|
; CHECK-LABEL: ctlz_4i32_0_t:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vclz.i32 q0, q0
|
|
; CHECK-NEXT: bx lr
|
|
entry:
|
|
%0 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 0)
|
|
ret <4 x i32> %0
|
|
}
|
|
|
|
define arm_aapcs_vfpcc <8 x i16> @ctlz_8i16_0_t(<8 x i16> %src){
|
|
; CHECK-LABEL: ctlz_8i16_0_t:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vclz.i16 q0, q0
|
|
; CHECK-NEXT: bx lr
|
|
entry:
|
|
%0 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 0)
|
|
ret <8 x i16> %0
|
|
}
|
|
|
|
define arm_aapcs_vfpcc <16 x i8> @ctlz_16i8_0_t(<16 x i8> %src){
|
|
; CHECK-LABEL: ctlz_16i8_0_t:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vclz.i8 q0, q0
|
|
; CHECK-NEXT: bx lr
|
|
entry:
|
|
%0 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 0)
|
|
ret <16 x i8> %0
|
|
}
|
|
|
|
define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_1_t(<2 x i64> %src){
|
|
; CHECK-LABEL: ctlz_2i64_1_t:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vmov r0, r1, d1
|
|
; CHECK-NEXT: clz r0, r0
|
|
; CHECK-NEXT: cmp r1, #0
|
|
; CHECK-NEXT: cset r2, ne
|
|
; CHECK-NEXT: adds r0, #32
|
|
; CHECK-NEXT: cmp r2, #0
|
|
; CHECK-NEXT: it ne
|
|
; CHECK-NEXT: clzne r0, r1
|
|
; CHECK-NEXT: vmov s6, r0
|
|
; CHECK-NEXT: vmov r0, r1, d0
|
|
; CHECK-NEXT: clz r0, r0
|
|
; CHECK-NEXT: cmp r1, #0
|
|
; CHECK-NEXT: cset r2, ne
|
|
; CHECK-NEXT: adds r0, #32
|
|
; CHECK-NEXT: cmp r2, #0
|
|
; CHECK-NEXT: it ne
|
|
; CHECK-NEXT: clzne r0, r1
|
|
; CHECK-NEXT: vmov s4, r0
|
|
; CHECK-NEXT: vldr s5, .LCPI4_0
|
|
; CHECK-NEXT: vmov.f32 s7, s5
|
|
; CHECK-NEXT: vmov q0, q1
|
|
; CHECK-NEXT: bx lr
|
|
; CHECK-NEXT: .p2align 2
|
|
; CHECK-NEXT: @ %bb.1:
|
|
; CHECK-NEXT: .LCPI4_0:
|
|
; CHECK-NEXT: .long 0x00000000 @ float 0
|
|
entry:
|
|
%0 = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %src, i1 1)
|
|
ret <2 x i64> %0
|
|
}
|
|
|
|
define arm_aapcs_vfpcc <4 x i32> @ctlz_4i32_1_t(<4 x i32> %src){
|
|
; CHECK-LABEL: ctlz_4i32_1_t:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vclz.i32 q0, q0
|
|
; CHECK-NEXT: bx lr
|
|
entry:
|
|
%0 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %src, i1 1)
|
|
ret <4 x i32> %0
|
|
}
|
|
|
|
define arm_aapcs_vfpcc <8 x i16> @ctlz_8i16_1_t(<8 x i16> %src){
|
|
; CHECK-LABEL: ctlz_8i16_1_t:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vclz.i16 q0, q0
|
|
; CHECK-NEXT: bx lr
|
|
entry:
|
|
%0 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %src, i1 1)
|
|
ret <8 x i16> %0
|
|
}
|
|
|
|
define arm_aapcs_vfpcc <16 x i8> @ctlz_16i8_1_t(<16 x i8> %src){
|
|
; CHECK-LABEL: ctlz_16i8_1_t:
|
|
; CHECK: @ %bb.0: @ %entry
|
|
; CHECK-NEXT: vclz.i8 q0, q0
|
|
; CHECK-NEXT: bx lr
|
|
entry:
|
|
%0 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %src, i1 1)
|
|
ret <16 x i8> %0
|
|
}
|
|
|
|
|
|
declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1)
|
|
declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1)
|
|
declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1)
|
|
declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1)
|