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dc98bdfb7d
This patch adds tablegen patterns for pairs of i16/f16 insert/extracts. If we are inserting into two adjacent vector lanes (0 and 1 for example), we can use either a vmov;vins or vmovx;vins to insert the pair together, avoiding a round-trip from GRP registers. This is quite a large patterns with a number of EXTRACT_SUBREG/INSERT_SUBREG/ COPY_TO_REGCLASS nodes, but hopefully as most of those become copies all that will be cleaned up by further optimizations. The VINS pattern was also adjusted to allow it to represent that it is inserting into the top half of an existing register. Differential Revision: https://reviews.llvm.org/D95381
154 lines
5.2 KiB
LLVM
154 lines
5.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
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define arm_aapcs_vfpcc <8 x half> @fneg_float16_t(<8 x half> %src) {
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; CHECK-MVE-LABEL: fneg_float16_t:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: vmov q1, q0
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; CHECK-MVE-NEXT: vmovx.f16 s0, s4
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; CHECK-MVE-NEXT: vneg.f16 s8, s0
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; CHECK-MVE-NEXT: vneg.f16 s0, s4
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; CHECK-MVE-NEXT: vins.f16 s0, s8
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; CHECK-MVE-NEXT: vmovx.f16 s8, s5
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; CHECK-MVE-NEXT: vneg.f16 s8, s8
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; CHECK-MVE-NEXT: vneg.f16 s1, s5
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; CHECK-MVE-NEXT: vins.f16 s1, s8
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; CHECK-MVE-NEXT: vmovx.f16 s8, s6
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; CHECK-MVE-NEXT: vneg.f16 s8, s8
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; CHECK-MVE-NEXT: vneg.f16 s2, s6
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; CHECK-MVE-NEXT: vins.f16 s2, s8
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; CHECK-MVE-NEXT: vmovx.f16 s8, s7
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; CHECK-MVE-NEXT: vneg.f16 s8, s8
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; CHECK-MVE-NEXT: vneg.f16 s3, s7
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; CHECK-MVE-NEXT: vins.f16 s3, s8
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-MVEFP-LABEL: fneg_float16_t:
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; CHECK-MVEFP: @ %bb.0: @ %entry
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; CHECK-MVEFP-NEXT: vneg.f16 q0, q0
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; CHECK-MVEFP-NEXT: bx lr
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entry:
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%0 = fsub nnan ninf nsz <8 x half> <half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0, half 0.0e0>, %src
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ret <8 x half> %0
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}
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define arm_aapcs_vfpcc <4 x float> @fneg_float32_t(<4 x float> %src) {
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; CHECK-MVE-LABEL: fneg_float32_t:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: vneg.f32 s7, s3
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; CHECK-MVE-NEXT: vneg.f32 s6, s2
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; CHECK-MVE-NEXT: vneg.f32 s5, s1
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; CHECK-MVE-NEXT: vneg.f32 s4, s0
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; CHECK-MVE-NEXT: vmov q0, q1
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-MVEFP-LABEL: fneg_float32_t:
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; CHECK-MVEFP: @ %bb.0: @ %entry
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; CHECK-MVEFP-NEXT: vneg.f32 q0, q0
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; CHECK-MVEFP-NEXT: bx lr
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entry:
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%0 = fsub nnan ninf nsz <4 x float> <float 0.0e0, float 0.0e0, float 0.0e0, float 0.0e0>, %src
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ret <4 x float> %0
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}
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define arm_aapcs_vfpcc <2 x double> @fneg_float64_t(<2 x double> %src) {
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; CHECK-LABEL: fneg_float64_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: .pad #16
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; CHECK-NEXT: sub sp, #16
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; CHECK-NEXT: vstr d1, [sp]
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; CHECK-NEXT: ldrb.w r0, [sp, #7]
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; CHECK-NEXT: vstr d0, [sp, #8]
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; CHECK-NEXT: ldrb.w r1, [sp, #15]
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; CHECK-NEXT: eor r0, r0, #128
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; CHECK-NEXT: strb.w r0, [sp, #7]
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; CHECK-NEXT: vldr d1, [sp]
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; CHECK-NEXT: eor r0, r1, #128
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; CHECK-NEXT: strb.w r0, [sp, #15]
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; CHECK-NEXT: vldr d0, [sp, #8]
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; CHECK-NEXT: add sp, #16
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; CHECK-NEXT: bx lr
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entry:
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%0 = fsub nnan ninf nsz <2 x double> <double 0.0e0, double 0.0e0>, %src
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ret <2 x double> %0
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}
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define arm_aapcs_vfpcc <8 x half> @fabs_float16_t(<8 x half> %src) {
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; CHECK-MVE-LABEL: fabs_float16_t:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: vmov q1, q0
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; CHECK-MVE-NEXT: vmovx.f16 s0, s4
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; CHECK-MVE-NEXT: vabs.f16 s8, s0
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; CHECK-MVE-NEXT: vabs.f16 s0, s4
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; CHECK-MVE-NEXT: vins.f16 s0, s8
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; CHECK-MVE-NEXT: vmovx.f16 s8, s5
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; CHECK-MVE-NEXT: vabs.f16 s8, s8
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; CHECK-MVE-NEXT: vabs.f16 s1, s5
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; CHECK-MVE-NEXT: vins.f16 s1, s8
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; CHECK-MVE-NEXT: vmovx.f16 s8, s6
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; CHECK-MVE-NEXT: vabs.f16 s8, s8
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; CHECK-MVE-NEXT: vabs.f16 s2, s6
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; CHECK-MVE-NEXT: vins.f16 s2, s8
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; CHECK-MVE-NEXT: vmovx.f16 s8, s7
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; CHECK-MVE-NEXT: vabs.f16 s8, s8
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; CHECK-MVE-NEXT: vabs.f16 s3, s7
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; CHECK-MVE-NEXT: vins.f16 s3, s8
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-MVEFP-LABEL: fabs_float16_t:
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; CHECK-MVEFP: @ %bb.0: @ %entry
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; CHECK-MVEFP-NEXT: vabs.f16 q0, q0
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; CHECK-MVEFP-NEXT: bx lr
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entry:
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%0 = call nnan ninf nsz <8 x half> @llvm.fabs.v8f16(<8 x half> %src)
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ret <8 x half> %0
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}
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define arm_aapcs_vfpcc <4 x float> @fabs_float32_t(<4 x float> %src) {
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; CHECK-MVE-LABEL: fabs_float32_t:
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; CHECK-MVE: @ %bb.0: @ %entry
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; CHECK-MVE-NEXT: vabs.f32 s7, s3
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; CHECK-MVE-NEXT: vabs.f32 s6, s2
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; CHECK-MVE-NEXT: vabs.f32 s5, s1
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; CHECK-MVE-NEXT: vabs.f32 s4, s0
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; CHECK-MVE-NEXT: vmov q0, q1
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; CHECK-MVE-NEXT: bx lr
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;
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; CHECK-MVEFP-LABEL: fabs_float32_t:
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; CHECK-MVEFP: @ %bb.0: @ %entry
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; CHECK-MVEFP-NEXT: vabs.f32 q0, q0
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; CHECK-MVEFP-NEXT: bx lr
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entry:
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%0 = call nnan ninf nsz <4 x float> @llvm.fabs.v4f32(<4 x float> %src)
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ret <4 x float> %0
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}
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define arm_aapcs_vfpcc <2 x double> @fabs_float64_t(<2 x double> %src) {
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; CHECK-LABEL: fabs_float64_t:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldr d2, .LCPI5_0
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; CHECK-NEXT: vmov r12, r3, d0
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; CHECK-NEXT: vmov r0, r1, d2
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; CHECK-NEXT: vmov r0, r2, d1
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; CHECK-NEXT: lsrs r1, r1, #31
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; CHECK-NEXT: bfi r2, r1, #31, #1
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; CHECK-NEXT: bfi r3, r1, #31, #1
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; CHECK-NEXT: vmov d1, r0, r2
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; CHECK-NEXT: vmov d0, r12, r3
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 3
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI5_0:
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; CHECK-NEXT: .long 0 @ double 0
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; CHECK-NEXT: .long 0
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entry:
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%0 = call nnan ninf nsz <2 x double> @llvm.fabs.v2f64(<2 x double> %src)
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ret <2 x double> %0
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}
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declare <4 x float> @llvm.fabs.v4f32(<4 x float>)
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declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
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declare <2 x double> @llvm.fabs.v2f64(<2 x double>)
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