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17e932c916
This adds a combine for extract(x, n); extract(x, n+1) -> VMOVRRD(extract x, n/2). This allows two vector lanes to be moved at the same time in a single instruction, and thanks to the other VMOVRRD folds we have added recently can help reduce the amount of executed instructions. Floating point types are very similar, but will include a bitcast to an integer type. This also adds a shouldRewriteCopySrc, to prevent copy propagation from DPR to SPR, which can break as not all DPR regs can be extracted from directly. Otherwise the machine verifier is unhappy. Differential Revision: https://reviews.llvm.org/D100244
52 lines
1.4 KiB
LLVM
52 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
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define arm_aapcs_vfpcc <16 x i8> @neg_v16i8(<16 x i8> %s1) {
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; CHECK-LABEL: neg_v16i8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vneg.s8 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = sub nsw <16 x i8> zeroinitializer, %s1
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ret <16 x i8> %0
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}
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define arm_aapcs_vfpcc <8 x i16> @neg_v8i16(<8 x i16> %s1) {
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; CHECK-LABEL: neg_v8i16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vneg.s16 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = sub nsw <8 x i16> zeroinitializer, %s1
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ret <8 x i16> %0
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}
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define arm_aapcs_vfpcc <4 x i32> @neg_v4i32(<4 x i32> %s1) {
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; CHECK-LABEL: neg_v4i32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vneg.s32 q0, q0
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; CHECK-NEXT: bx lr
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entry:
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%0 = sub nsw <4 x i32> zeroinitializer, %s1
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <2 x i64> @neg_v2i64(<2 x i64> %s1) {
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; CHECK-LABEL: neg_v2i64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov r0, r1, d1
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; CHECK-NEXT: mov.w r12, #0
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; CHECK-NEXT: vmov r3, r2, d0
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; CHECK-NEXT: rsbs r0, r0, #0
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; CHECK-NEXT: sbc.w r1, r12, r1
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; CHECK-NEXT: rsbs r3, r3, #0
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; CHECK-NEXT: sbc.w r2, r12, r2
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; CHECK-NEXT: vmov q0[2], q0[0], r3, r0
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; CHECK-NEXT: vmov q0[3], q0[1], r2, r1
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; CHECK-NEXT: bx lr
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entry:
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%0 = sub nsw <2 x i64> zeroinitializer, %s1
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ret <2 x i64> %0
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}
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