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17e932c916
This adds a combine for extract(x, n); extract(x, n+1) -> VMOVRRD(extract x, n/2). This allows two vector lanes to be moved at the same time in a single instruction, and thanks to the other VMOVRRD folds we have added recently can help reduce the amount of executed instructions. Floating point types are very similar, but will include a bitcast to an integer type. This also adds a shouldRewriteCopySrc, to prevent copy propagation from DPR to SPR, which can break as not all DPR regs can be extracted from directly. Otherwise the machine verifier is unhappy. Differential Revision: https://reviews.llvm.org/D100244
140 lines
5.1 KiB
LLVM
140 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve,-vfp2 -o - %s | FileCheck %s --check-prefix=CHECK-NOFP
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; RUN: llc -mtriple=thumbv8.1m.main-none-eabi -mattr=+mve.fp -o - %s | FileCheck --check-prefix=CHECK-FP %s
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; This file tests tests that we expand floating point operations correctly,
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; even if we do not have an fpu.
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define arm_aapcs_vfpcc <8 x half> @vector_add_f16(<8 x half> %lhs, <8 x half> %rhs) {
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; CHECK-NOFP-LABEL: vector_add_f16:
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; CHECK-NOFP: @ %bb.0: @ %entry
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; CHECK-NOFP-NEXT: .save {r4, lr}
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; CHECK-NOFP-NEXT: push {r4, lr}
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; CHECK-NOFP-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
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; CHECK-NOFP-NEXT: vpush {d8, d9, d10, d11, d12, d13}
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; CHECK-NOFP-NEXT: vmov.u16 r0, q1[0]
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; CHECK-NOFP-NEXT: vmov q5, q1
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; CHECK-NOFP-NEXT: vmov q4, q0
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; CHECK-NOFP-NEXT: bl __aeabi_h2f
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; CHECK-NOFP-NEXT: mov r4, r0
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; CHECK-NOFP-NEXT: vmov.u16 r0, q4[0]
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; CHECK-NOFP-NEXT: bl __aeabi_h2f
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; CHECK-NOFP-NEXT: mov r1, r4
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; CHECK-NOFP-NEXT: bl __aeabi_fadd
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; CHECK-NOFP-NEXT: bl __aeabi_f2h
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; CHECK-NOFP-NEXT: vmov.16 q6[0], r0
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; CHECK-NOFP-NEXT: vmov.u16 r0, q5[1]
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; CHECK-NOFP-NEXT: bl __aeabi_h2f
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; CHECK-NOFP-NEXT: mov r4, r0
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; CHECK-NOFP-NEXT: vmov.u16 r0, q4[1]
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; CHECK-NOFP-NEXT: bl __aeabi_h2f
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; CHECK-NOFP-NEXT: mov r1, r4
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; CHECK-NOFP-NEXT: bl __aeabi_fadd
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; CHECK-NOFP-NEXT: bl __aeabi_f2h
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; CHECK-NOFP-NEXT: vmov.16 q6[1], r0
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; CHECK-NOFP-NEXT: vmov.u16 r0, q5[2]
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; CHECK-NOFP-NEXT: bl __aeabi_h2f
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; CHECK-NOFP-NEXT: mov r4, r0
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; CHECK-NOFP-NEXT: vmov.u16 r0, q4[2]
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; CHECK-NOFP-NEXT: bl __aeabi_h2f
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; CHECK-NOFP-NEXT: mov r1, r4
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; CHECK-NOFP-NEXT: bl __aeabi_fadd
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; CHECK-NOFP-NEXT: bl __aeabi_f2h
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; CHECK-NOFP-NEXT: vmov.16 q6[2], r0
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; CHECK-NOFP-NEXT: vmov.u16 r0, q5[3]
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; CHECK-NOFP-NEXT: bl __aeabi_h2f
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; CHECK-NOFP-NEXT: mov r4, r0
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; CHECK-NOFP-NEXT: vmov.u16 r0, q4[3]
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; CHECK-NOFP-NEXT: bl __aeabi_h2f
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; CHECK-NOFP-NEXT: mov r1, r4
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; CHECK-NOFP-NEXT: bl __aeabi_fadd
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; CHECK-NOFP-NEXT: bl __aeabi_f2h
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; CHECK-NOFP-NEXT: vmov.16 q6[3], r0
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; CHECK-NOFP-NEXT: vmov.u16 r0, q5[4]
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; CHECK-NOFP-NEXT: bl __aeabi_h2f
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; CHECK-NOFP-NEXT: mov r4, r0
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; CHECK-NOFP-NEXT: vmov.u16 r0, q4[4]
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; CHECK-NOFP-NEXT: bl __aeabi_h2f
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; CHECK-NOFP-NEXT: mov r1, r4
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; CHECK-NOFP-NEXT: bl __aeabi_fadd
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; CHECK-NOFP-NEXT: bl __aeabi_f2h
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; CHECK-NOFP-NEXT: vmov.16 q6[4], r0
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; CHECK-NOFP-NEXT: vmov.u16 r0, q5[5]
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; CHECK-NOFP-NEXT: bl __aeabi_h2f
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; CHECK-NOFP-NEXT: mov r4, r0
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; CHECK-NOFP-NEXT: vmov.u16 r0, q4[5]
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; CHECK-NOFP-NEXT: bl __aeabi_h2f
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; CHECK-NOFP-NEXT: mov r1, r4
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; CHECK-NOFP-NEXT: bl __aeabi_fadd
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; CHECK-NOFP-NEXT: bl __aeabi_f2h
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; CHECK-NOFP-NEXT: vmov.16 q6[5], r0
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; CHECK-NOFP-NEXT: vmov.u16 r0, q5[6]
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; CHECK-NOFP-NEXT: bl __aeabi_h2f
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; CHECK-NOFP-NEXT: mov r4, r0
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; CHECK-NOFP-NEXT: vmov.u16 r0, q4[6]
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; CHECK-NOFP-NEXT: bl __aeabi_h2f
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; CHECK-NOFP-NEXT: mov r1, r4
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; CHECK-NOFP-NEXT: bl __aeabi_fadd
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; CHECK-NOFP-NEXT: bl __aeabi_f2h
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; CHECK-NOFP-NEXT: vmov.16 q6[6], r0
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; CHECK-NOFP-NEXT: vmov.u16 r0, q5[7]
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; CHECK-NOFP-NEXT: bl __aeabi_h2f
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; CHECK-NOFP-NEXT: mov r4, r0
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; CHECK-NOFP-NEXT: vmov.u16 r0, q4[7]
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; CHECK-NOFP-NEXT: bl __aeabi_h2f
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; CHECK-NOFP-NEXT: mov r1, r4
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; CHECK-NOFP-NEXT: bl __aeabi_fadd
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; CHECK-NOFP-NEXT: bl __aeabi_f2h
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; CHECK-NOFP-NEXT: vmov.16 q6[7], r0
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; CHECK-NOFP-NEXT: vmov q0, q6
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; CHECK-NOFP-NEXT: vpop {d8, d9, d10, d11, d12, d13}
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; CHECK-NOFP-NEXT: pop {r4, pc}
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;
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; CHECK-FP-LABEL: vector_add_f16:
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; CHECK-FP: @ %bb.0: @ %entry
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; CHECK-FP-NEXT: vadd.f16 q0, q0, q1
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; CHECK-FP-NEXT: bx lr
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entry:
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%sum = fadd <8 x half> %lhs, %rhs
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ret <8 x half> %sum
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}
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define arm_aapcs_vfpcc <4 x float> @vector_add_f32(<4 x float> %lhs, <4 x float> %rhs) {
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; CHECK-NOFP-LABEL: vector_add_f32:
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; CHECK-NOFP: @ %bb.0: @ %entry
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; CHECK-NOFP-NEXT: .save {r4, r5, r7, lr}
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; CHECK-NOFP-NEXT: push {r4, r5, r7, lr}
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; CHECK-NOFP-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
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; CHECK-NOFP-NEXT: vpush {d8, d9, d10, d11, d12, d13}
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; CHECK-NOFP-NEXT: vmov q5, q1
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; CHECK-NOFP-NEXT: vmov q6, q0
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; CHECK-NOFP-NEXT: vmov r4, r0, d13
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; CHECK-NOFP-NEXT: vmov r5, r1, d11
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; CHECK-NOFP-NEXT: bl __aeabi_fadd
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; CHECK-NOFP-NEXT: vmov s19, r0
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; CHECK-NOFP-NEXT: mov r0, r4
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; CHECK-NOFP-NEXT: mov r1, r5
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; CHECK-NOFP-NEXT: bl __aeabi_fadd
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; CHECK-NOFP-NEXT: vmov s18, r0
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; CHECK-NOFP-NEXT: vmov r4, r0, d12
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; CHECK-NOFP-NEXT: vmov r5, r1, d10
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; CHECK-NOFP-NEXT: bl __aeabi_fadd
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; CHECK-NOFP-NEXT: vmov s17, r0
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; CHECK-NOFP-NEXT: mov r0, r4
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; CHECK-NOFP-NEXT: mov r1, r5
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; CHECK-NOFP-NEXT: bl __aeabi_fadd
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; CHECK-NOFP-NEXT: vmov s16, r0
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; CHECK-NOFP-NEXT: vmov q0, q4
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; CHECK-NOFP-NEXT: vpop {d8, d9, d10, d11, d12, d13}
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; CHECK-NOFP-NEXT: pop {r4, r5, r7, pc}
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;
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; CHECK-FP-LABEL: vector_add_f32:
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; CHECK-FP: @ %bb.0: @ %entry
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; CHECK-FP-NEXT: vadd.f32 q0, q0, q1
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; CHECK-FP-NEXT: bx lr
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entry:
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%sum = fadd <4 x float> %lhs, %rhs
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ret <4 x float> %sum
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}
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