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llvm-mirror/test/CodeGen/Thumb2/mve-vldst4.ll
Tomas Matheson bb84fe4048 [CodeGen][regalloc] Don't align stack slots if the stack can't be realigned 
Register allocation may spill virtual registers to the stack, which can
increase alignment requirements of the stack frame. If the the function
did not require stack realignment before register allocation, the
registers required to do so may not be reserved/available. This results
in a stack frame that requires realignment but can not be realigned.

Instead, only increase the alignment of the stack if we are still able
to realign.

The register SpillAlignment will be ignored if we can't realign, and the
backend will be responsible for emitting the correct unaligned loads and
stores. This seems to be the assumed behaviour already, e.g.
ARMBaseInstrInfo::storeRegToStackSlot and X86InstrInfo::storeRegToStackSlot
are both `canRealignStack` aware.

Differential Revision: https://reviews.llvm.org/D103602
2021-06-11 16:49:12 +01:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s
define void @vldst4(half* nocapture readonly %pIn, half* nocapture %pOut, i32 %numRows, i32 %numCols, i32 %scale.coerce) #0 {
; CHECK-LABEL: vldst4:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r7, lr}
; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: .pad #16
; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: mul r12, r3, r2
; CHECK-NEXT: lsrs.w r2, r12, #2
; CHECK-NEXT: beq.w .LBB0_3
; CHECK-NEXT: @ %bb.1: @ %vector.ph
; CHECK-NEXT: mvn r3, #7
; CHECK-NEXT: ldr r2, [sp, #88]
; CHECK-NEXT: and.w r3, r3, r12, lsr #2
; CHECK-NEXT: sub.w r12, r3, #8
; CHECK-NEXT: movs r3, #1
; CHECK-NEXT: add.w lr, r3, r12, lsr #3
; CHECK-NEXT: .LBB0_2: @ %vector.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u16 q4, [r0, #32]
; CHECK-NEXT: vldrh.u16 q5, [r0, #48]
; CHECK-NEXT: vldrh.u16 q3, [r0], #64
; CHECK-NEXT: vmov.f32 s2, s17
; CHECK-NEXT: vmovx.f16 s8, s19
; CHECK-NEXT: vldrh.u16 q6, [r0, #-48]
; CHECK-NEXT: vins.f16 s2, s19
; CHECK-NEXT: vmov.f32 s3, s21
; CHECK-NEXT: vmovx.f16 s5, s25
; CHECK-NEXT: vins.f16 s3, s23
; CHECK-NEXT: vmovx.f16 s6, s17
; CHECK-NEXT: vmov.f32 s0, s13
; CHECK-NEXT: vins.f16 s6, s8
; CHECK-NEXT: vmovx.f16 s8, s23
; CHECK-NEXT: vmovx.f16 s7, s21
; CHECK-NEXT: vins.f16 s0, s15
; CHECK-NEXT: vins.f16 s7, s8
; CHECK-NEXT: vmovx.f16 s8, s15
; CHECK-NEXT: vmovx.f16 s4, s13
; CHECK-NEXT: vins.f16 s25, s27
; CHECK-NEXT: vins.f16 s4, s8
; CHECK-NEXT: vmovx.f16 s8, s27
; CHECK-NEXT: vins.f16 s5, s8
; CHECK-NEXT: vmov.f32 s1, s25
; CHECK-NEXT: vmul.f16 q2, q1, r2
; CHECK-NEXT: vmul.f16 q0, q0, r2
; CHECK-NEXT: vmovx.f16 s7, s0
; CHECK-NEXT: vmovx.f16 s28, s8
; CHECK-NEXT: vins.f16 s7, s28
; CHECK-NEXT: vmovx.f16 s30, s16
; CHECK-NEXT: vmovx.f16 s31, s20
; CHECK-NEXT: vstrw.32 q1, [sp] @ 16-byte Spill
; CHECK-NEXT: vmovx.f16 s28, s12
; CHECK-NEXT: vins.f16 s16, s18
; CHECK-NEXT: vmovx.f16 s29, s24
; CHECK-NEXT: vmovx.f16 s4, s18
; CHECK-NEXT: vins.f16 s20, s22
; CHECK-NEXT: vins.f16 s30, s4
; CHECK-NEXT: vmovx.f16 s4, s22
; CHECK-NEXT: vins.f16 s12, s14
; CHECK-NEXT: vins.f16 s31, s4
; CHECK-NEXT: vmovx.f16 s4, s14
; CHECK-NEXT: vmov.f32 s14, s16
; CHECK-NEXT: vins.f16 s24, s26
; CHECK-NEXT: vmov.f32 s15, s20
; CHECK-NEXT: vins.f16 s28, s4
; CHECK-NEXT: vmovx.f16 s4, s26
; CHECK-NEXT: vmov.f32 s13, s24
; CHECK-NEXT: vins.f16 s29, s4
; CHECK-NEXT: vmul.f16 q3, q3, r2
; CHECK-NEXT: vmul.f16 q7, q7, r2
; CHECK-NEXT: vmovx.f16 s4, s12
; CHECK-NEXT: vmovx.f16 s6, s28
; CHECK-NEXT: vins.f16 s0, s8
; CHECK-NEXT: vins.f16 s4, s6
; CHECK-NEXT: vmovx.f16 s6, s1
; CHECK-NEXT: vmovx.f16 s5, s9
; CHECK-NEXT: vins.f16 s12, s28
; CHECK-NEXT: vins.f16 s6, s5
; CHECK-NEXT: vmovx.f16 s18, s13
; CHECK-NEXT: vmovx.f16 s5, s29
; CHECK-NEXT: vins.f16 s1, s9
; CHECK-NEXT: vins.f16 s18, s5
; CHECK-NEXT: vmovx.f16 s23, s2
; CHECK-NEXT: vmovx.f16 s5, s10
; CHECK-NEXT: vins.f16 s2, s10
; CHECK-NEXT: vins.f16 s23, s5
; CHECK-NEXT: vins.f16 s13, s29
; CHECK-NEXT: vmovx.f16 s27, s3
; CHECK-NEXT: vmovx.f16 s8, s11
; CHECK-NEXT: vmovx.f16 s22, s14
; CHECK-NEXT: vins.f16 s27, s8
; CHECK-NEXT: vins.f16 s14, s30
; CHECK-NEXT: vmovx.f16 s26, s15
; CHECK-NEXT: vins.f16 s15, s31
; CHECK-NEXT: vmovx.f16 s8, s31
; CHECK-NEXT: vins.f16 s3, s11
; CHECK-NEXT: vins.f16 s26, s8
; CHECK-NEXT: vmov q2, q3
; CHECK-NEXT: vmovx.f16 s5, s30
; CHECK-NEXT: vldrw.u32 q7, [sp] @ 16-byte Reload
; CHECK-NEXT: vmov.f32 s10, s4
; CHECK-NEXT: vmov.f32 s29, s0
; CHECK-NEXT: vins.f16 s22, s5
; CHECK-NEXT: vmov.f32 s9, s0
; CHECK-NEXT: vmov.f32 s11, s31
; CHECK-NEXT: vmov q7, q0
; CHECK-NEXT: vmov.f32 s31, s6
; CHECK-NEXT: vmov.f32 s16, s13
; CHECK-NEXT: vmov.f32 s21, s2
; CHECK-NEXT: vmov.f32 s25, s3
; CHECK-NEXT: vmov.f32 s17, s29
; CHECK-NEXT: vmov.f32 s20, s14
; CHECK-NEXT: vmov.f32 s24, s15
; CHECK-NEXT: vstrh.16 q5, [r1, #32]
; CHECK-NEXT: vstrh.16 q6, [r1, #48]
; CHECK-NEXT: vstrh.16 q2, [r1], #64
; CHECK-NEXT: vmov.f32 s19, s31
; CHECK-NEXT: vstrh.16 q4, [r1, #-48]
; CHECK-NEXT: le lr, .LBB0_2
; CHECK-NEXT: .LBB0_3: @ %while.end
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: pop {r7, pc}
entry:
%tmp.0.extract.trunc = trunc i32 %scale.coerce to i16
%l0 = bitcast i16 %tmp.0.extract.trunc to half
%mul = mul i32 %numCols, %numRows
%shr = lshr i32 %mul, 2
%cmp38 = icmp eq i32 %shr, 0
br i1 %cmp38, label %while.end, label %vector.ph
vector.ph: ; preds = %vector.memcheck
%n.vec = and i32 %shr, 1073741816
%l2 = shl nuw i32 %n.vec, 2
%ind.end = getelementptr half, half* %pIn, i32 %l2
%l3 = shl nuw i32 %n.vec, 2
%ind.end48 = getelementptr half, half* %pOut, i32 %l3
%ind.end50 = sub nsw i32 %shr, %n.vec
%broadcast.splatinsert55 = insertelement <8 x half> undef, half %l0, i32 0
%broadcast.splat56 = shufflevector <8 x half> %broadcast.splatinsert55, <8 x half> undef, <8 x i32> zeroinitializer
br label %vector.body
vector.body: ; preds = %vector.body, %vector.ph
%index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]
%l4 = shl i32 %index, 2
%next.gep = getelementptr half, half* %pIn, i32 %l4
%l5 = shl i32 %index, 2
%l6 = bitcast half* %next.gep to <32 x half>*
%wide.vec = load <32 x half>, <32 x half>* %l6, align 2
%strided.vec = shufflevector <32 x half> %wide.vec, <32 x half> undef, <8 x i32> <i32 0, i32 4, i32 8, i32 12, i32 16, i32 20, i32 24, i32 28>
%strided.vec52 = shufflevector <32 x half> %wide.vec, <32 x half> undef, <8 x i32> <i32 1, i32 5, i32 9, i32 13, i32 17, i32 21, i32 25, i32 29>
%strided.vec53 = shufflevector <32 x half> %wide.vec, <32 x half> undef, <8 x i32> <i32 2, i32 6, i32 10, i32 14, i32 18, i32 22, i32 26, i32 30>
%strided.vec54 = shufflevector <32 x half> %wide.vec, <32 x half> undef, <8 x i32> <i32 3, i32 7, i32 11, i32 15, i32 19, i32 23, i32 27, i32 31>
%l7 = fmul <8 x half> %strided.vec, %broadcast.splat56
%l8 = fmul <8 x half> %strided.vec52, %broadcast.splat56
%l9 = fmul <8 x half> %strided.vec53, %broadcast.splat56
%l10 = fmul <8 x half> %strided.vec54, %broadcast.splat56
%l11 = getelementptr inbounds half, half* %pOut, i32 %l5
%l12 = bitcast half* %l11 to <32 x half>*
%l13 = shufflevector <8 x half> %l7, <8 x half> %l8, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%l14 = shufflevector <8 x half> %l9, <8 x half> %l10, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
%interleaved.vec = shufflevector <16 x half> %l13, <16 x half> %l14, <32 x i32> <i32 0, i32 8, i32 16, i32 24, i32 1, i32 9, i32 17, i32 25, i32 2, i32 10, i32 18, i32 26, i32 3, i32 11, i32 19, i32 27, i32 4, i32 12, i32 20, i32 28, i32 5, i32 13, i32 21, i32 29, i32 6, i32 14, i32 22, i32 30, i32 7, i32 15, i32 23, i32 31>
store <32 x half> %interleaved.vec, <32 x half>* %l12, align 2
%index.next = add i32 %index, 8
%l15 = icmp eq i32 %index.next, %n.vec
br i1 %l15, label %while.end, label %vector.body
while.end: ; preds = %while.body, %middle.block, %entry
ret void
}
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