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9a4c805887
When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. This patch is for STWU/STWUX (IIC_LdStStoreUpd ) for P8. Since there are already multiple IIC for store update, this patch also merge IIC_LdStSTDU/IIC_LdStStoreUpd to IIC_LdStSTU IIC_LdStSTDUX to IIC_LdStSTUX and we add a new testcase in https://reviews.llvm.org/D54699 to show the difference. Differential Revision: https://reviews.llvm.org/D54700 llvm-svn: 347311
140 lines
5.1 KiB
TableGen
140 lines
5.1 KiB
TableGen
//===-- PPCSchedule.td - PowerPC Scheduling Definitions ----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for PowerPC
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//
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def IIC_IntSimple : InstrItinClass;
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def IIC_IntGeneral : InstrItinClass;
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def IIC_IntCompare : InstrItinClass;
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def IIC_IntISEL : InstrItinClass;
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def IIC_IntDivD : InstrItinClass;
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def IIC_IntDivW : InstrItinClass;
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def IIC_IntMFFS : InstrItinClass;
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def IIC_IntMFVSCR : InstrItinClass;
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def IIC_IntMTFSB0 : InstrItinClass;
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def IIC_IntMTSRD : InstrItinClass;
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def IIC_IntMulHD : InstrItinClass;
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def IIC_IntMulHW : InstrItinClass;
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def IIC_IntMulHWU : InstrItinClass;
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def IIC_IntMulLI : InstrItinClass;
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def IIC_IntRFID : InstrItinClass;
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def IIC_IntRotateD : InstrItinClass;
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def IIC_IntRotateDI : InstrItinClass;
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def IIC_IntRotate : InstrItinClass;
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def IIC_IntShift : InstrItinClass;
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def IIC_IntTrapD : InstrItinClass;
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def IIC_IntTrapW : InstrItinClass;
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def IIC_BrB : InstrItinClass;
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def IIC_BrCR : InstrItinClass;
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def IIC_BrMCR : InstrItinClass;
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def IIC_BrMCRX : InstrItinClass;
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def IIC_LdStDCBA : InstrItinClass;
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def IIC_LdStDCBF : InstrItinClass;
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def IIC_LdStDCBI : InstrItinClass;
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def IIC_LdStLoad : InstrItinClass;
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def IIC_LdStLoadUpd : InstrItinClass;
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def IIC_LdStLoadUpdX : InstrItinClass;
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def IIC_LdStStore : InstrItinClass;
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def IIC_LdStDSS : InstrItinClass;
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def IIC_LdStICBI : InstrItinClass;
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def IIC_LdStLD : InstrItinClass;
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def IIC_LdStLDU : InstrItinClass;
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def IIC_LdStLDUX : InstrItinClass;
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def IIC_LdStLDARX : InstrItinClass;
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def IIC_LdStLFD : InstrItinClass;
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def IIC_LdStLFDU : InstrItinClass;
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def IIC_LdStLFDUX : InstrItinClass;
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def IIC_LdStLHA : InstrItinClass;
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def IIC_LdStLHAU : InstrItinClass;
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def IIC_LdStLHAUX : InstrItinClass;
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def IIC_LdStLMW : InstrItinClass;
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def IIC_LdStLVecX : InstrItinClass;
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def IIC_LdStLWA : InstrItinClass;
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def IIC_LdStLWARX : InstrItinClass;
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def IIC_LdStSLBIA : InstrItinClass;
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def IIC_LdStSLBIE : InstrItinClass;
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def IIC_LdStSTD : InstrItinClass;
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def IIC_LdStSTDCX : InstrItinClass;
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def IIC_LdStSTU : InstrItinClass;
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def IIC_LdStSTUX : InstrItinClass;
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def IIC_LdStSTFD : InstrItinClass;
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def IIC_LdStSTFDU : InstrItinClass;
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def IIC_LdStSTVEBX : InstrItinClass;
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def IIC_LdStSTWCX : InstrItinClass;
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def IIC_LdStSync : InstrItinClass;
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def IIC_LdStCOPY : InstrItinClass;
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def IIC_LdStPASTE : InstrItinClass;
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def IIC_SprISYNC : InstrItinClass;
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def IIC_SprMFSR : InstrItinClass;
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def IIC_SprMTMSR : InstrItinClass;
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def IIC_SprMTSR : InstrItinClass;
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def IIC_SprTLBSYNC : InstrItinClass;
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def IIC_SprMFCR : InstrItinClass;
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def IIC_SprMFCRF : InstrItinClass;
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def IIC_SprMFMSR : InstrItinClass;
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def IIC_SprMFSPR : InstrItinClass;
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def IIC_SprMFTB : InstrItinClass;
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def IIC_SprMTSPR : InstrItinClass;
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def IIC_SprMTSRIN : InstrItinClass;
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def IIC_SprRFI : InstrItinClass;
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def IIC_SprSC : InstrItinClass;
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def IIC_FPGeneral : InstrItinClass;
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def IIC_FPDGeneral : InstrItinClass;
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def IIC_FPSGeneral : InstrItinClass;
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def IIC_FPAddSub : InstrItinClass;
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def IIC_FPCompare : InstrItinClass;
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def IIC_FPDivD : InstrItinClass;
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def IIC_FPDivS : InstrItinClass;
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def IIC_FPFused : InstrItinClass;
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def IIC_FPRes : InstrItinClass;
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def IIC_FPSqrtD : InstrItinClass;
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def IIC_FPSqrtS : InstrItinClass;
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def IIC_VecGeneral : InstrItinClass;
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def IIC_VecFP : InstrItinClass;
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def IIC_VecFPCompare : InstrItinClass;
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def IIC_VecComplex : InstrItinClass;
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def IIC_VecPerm : InstrItinClass;
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def IIC_VecFPRound : InstrItinClass;
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def IIC_VecVSL : InstrItinClass;
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def IIC_VecVSR : InstrItinClass;
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def IIC_SprMTMSRD : InstrItinClass;
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def IIC_SprSLIE : InstrItinClass;
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def IIC_SprSLBIE : InstrItinClass;
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def IIC_SprSLBIEG : InstrItinClass;
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def IIC_SprSLBMTE : InstrItinClass;
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def IIC_SprSLBMFEE : InstrItinClass;
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def IIC_SprSLBMFEV : InstrItinClass;
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def IIC_SprSLBIA : InstrItinClass;
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def IIC_SprSLBSYNC : InstrItinClass;
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def IIC_SprTLBIA : InstrItinClass;
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def IIC_SprTLBIEL : InstrItinClass;
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def IIC_SprTLBIE : InstrItinClass;
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def IIC_SprABORT : InstrItinClass;
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def IIC_SprMSGSYNC : InstrItinClass;
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def IIC_SprSTOP : InstrItinClass;
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def IIC_SprMFPMR : InstrItinClass;
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def IIC_SprMTPMR : InstrItinClass;
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//===----------------------------------------------------------------------===//
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// Processor instruction itineraries.
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include "PPCScheduleG3.td"
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include "PPCSchedule440.td"
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include "PPCScheduleG4.td"
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include "PPCScheduleG4Plus.td"
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include "PPCScheduleG5.td"
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include "PPCScheduleP7.td"
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include "PPCScheduleP8.td"
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include "PPCScheduleP9.td"
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include "PPCScheduleA2.td"
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include "PPCScheduleE500.td"
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include "PPCScheduleE500mc.td"
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include "PPCScheduleE5500.td"
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