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a49054ac9c
The fpscr register contains both flags (set by FP operations/comparisons) and control bits. The control bits (FPSCR) should be reserved, since they're always available and needn't be defined before use. The flag bits (FPSCR_NZCV) should like to be unreserved so they can be hoisted by MachineCSE. This fixes PR12165. llvm-svn: 152076
37 lines
1.1 KiB
LLVM
37 lines
1.1 KiB
LLVM
; RUN: llc -march=arm -mcpu=cortex-a8 -verify-machineinstrs < %s
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; PR12165
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target datalayout = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-p:32:32:32-v128:32:32"
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target triple = "arm-none-linux"
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define hidden void @_strtod_r() nounwind {
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br i1 undef, label %1, label %2
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; <label>:1 ; preds = %0
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br label %2
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; <label>:2 ; preds = %1, %0
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br i1 undef, label %3, label %8
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; <label>:3 ; preds = %2
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br i1 undef, label %4, label %7
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; <label>:4 ; preds = %3
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%5 = call i32 @llvm.flt.rounds()
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%6 = icmp eq i32 %5, 1
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br i1 %6, label %8, label %7
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; <label>:7 ; preds = %4, %3
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unreachable
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; <label>:8 ; preds = %4, %2
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br i1 undef, label %9, label %10
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; <label>:9 ; preds = %8
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br label %10
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; <label>:10 ; preds = %9, %8
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ret void
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}
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declare i32 @llvm.flt.rounds() nounwind
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