Jay Foad abd0bfe722 [AMDGPU] Set SchedRW on real instructions ... Coyp SchedRW from pseudos to real instructions so that llvm-mca has access to it. This is NFC for normal compiler codegen, which schedules pseudos not real instructions. Add an llvm-mca test for some high latency double-precision instructions as a smoke test. Differential Revision: https://reviews.llvm.org/D99187		2021-03-23 15:38:11 +00:00
..
Analysis	[IR][SVE] Add new llvm.experimental.stepvector intrinsic	2021-03-23 10:43:35 +00:00
Assembler
Bindings
Bitcode
BugPoint
CodeGen	[RISCV] Further optimize BUILD_VECTORs with repeated elements	2021-03-23 14:14:48 +00:00
DebugInfo	[llvm-symbolizer][llvm-nm] Fix AArch64 and ARM mapping symbols handling.	2021-03-23 14:17:12 +01:00
Demangle
Examples
ExecutionEngine	Temporarily revert "[lli] Make -jit-kind=orc the default JIT engine"	2021-03-23 12:01:30 +01:00
Feature
FileCheck
Instrumentation	[SanitizerCoverage] Use External on Windows	2021-03-22 23:05:36 -07:00
Integer	Temporarily revert "[lli] Make -jit-kind=orc the default JIT engine"	2021-03-23 12:01:30 +01:00
JitListener
Linker
LTO
MachineVerifier
MC
Object
ObjectYAML
Other	Revert "A new option -print-on-crash that prints the IR as it was upon entering the last pass when there is a crash."	2021-03-23 10:09:27 -04:00
Reduce
SafepointIRVerifier
Support
SymbolRewriter
TableGen	[openacc][openmp] Reduce number of generated file and prefer inclusion of .inc	2021-03-23 09:16:53 -04:00
ThinLTO/X86
tools	[AMDGPU] Set SchedRW on real instructions	2021-03-23 15:38:11 +00:00
Transforms	[PhaseOrdering] add AVX attribute to make test less fragile; NFC	2021-03-23 11:34:33 -04:00
Unit
Verifier	[IR][SVE] Add new llvm.experimental.stepvector intrinsic	2021-03-23 10:43:35 +00:00
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg.py
lit.site.cfg.py.in
TestRunner.sh